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1. description the M306H2MC-XXXFP is single-chip microcomputer using the high-performance silicon gate cmos pro- cess using a m16c/60 series cpu core and is packaged in a 116-pin plastic molded qfp. this single-chip microcomputer operates using sophisticated instructions featuring a high level of instruction efficiency. with 1m bytes of address space, this is capable of executing instructions at high speed. this also features a built-in data acquisition circuit, making this correspondence to teletext broadcasting service. 1.1 features ?memory capacity.................................. 128k bytes 5k bytes ?shortest instruction execution time ...... 100 ns (f(x in )=10 mhz) ?supply voltage ..................................... 4.75 v to 5.25v(at f(x in )=10 mhz) 2.80v to 5.25v(at f(x cin )=32kh z , only in low power dissipation mode) ?interrupts .............................................. 25 internal and 8 external interrupt sources, 4 software interrupt sources; 7 levels (including key input interrupt) ?multifunction 16-bit timer ...................... 5 output timers + 6 input timers ?serial i/o .............................................. 5 channels uart/clock synchronous: 3 clock synchronous: 2 ?dmac .................................................. 2 channels (trigger: 24 sources) ?a-d converter ....................................... 8 bits x 8 channels (expandable up to 10 channels) ?d-a converter ....................................... 8 bits x 2 channels ?crc calculation circuit ......................... 1 circuit ?watchdog timer .................................... 1 line ?programmable i/o ............................... 87 lines ?input port .............................................. _______ 1 port (p8 5 shared with nmi pin) ?output port ........................................... 1 port (p11 shared with sliceon pin) ?chip select output ................................ 4 lines ?clock generating circuit ....................... 2 built-in circuits (built-in feedback resistor, and external ceramic or crystal oscillator) ?data acquisition circuit ......................... for pdc, vps, epg-j, xds and wss 1.2 applications vcr, etc rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP
2 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP table of contents 1. description ...................................................... 1 1.1 features ........................................................... 1 1.2 applications ..................................................... 1 1.3 pin configuration ............................................. 3 1.4 block diagram ................................................. 4 1.5 performance outline ........................................ 5 2. operation of functional blocks ............ 9 2.1 memory ............................................................ 9 2.2 central processing unit (cpu) ........................ 13 2.3 reset ............................................................... 16 2.4 processor mode ............................................... 20 2.5 clock generating circuit .................................. 31 2.6 protection ......................................................... 40 2.7 interrupt ........................................................... 41 2.8 watchdog timer .............................................. 61 2.9 dmac .............................................................. 63 2.10 timer .............................................................. 73 2.11 serial i/o ........................................................ 91 2.12 a-d converter ................................................ 132 2.13 d-a converter ................................................ 142 2.14 crc calculation circuit ................................. 144 2.15 expansion function ....................................... 146 2.16 programmable i/o ports ................................ 170 3. usage precaution .......................................... 180 4. electrical characteristics ...................... 185 5. item to be submitted when ordering masked rom version ......... 203 6. package outline ............................................. 204 7. differences between M306H2MC-XXXFP and m306h2fcfp .... 205
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 3 rev. 1.0 M306H2MC-XXXFP b y t e x o u t v s s x i n v c c p 8 7 / x c i n p 8 6 / x c o u t p 8 1 / t a 4 i n p 8 0 / t a 4 o u t p 7 7 / t a 3 i n c n v s s p 9 0 / t b 0 i n / c l k 3 p 9 1 / t b 1 i n / s i n 3 p 9 2 / t b 2 i n / s o u t 3 p 9 4 / d a 1 / t b 4 i n p 9 5 / a n e x 0 / c l k 4 p 9 3 / d a 0 / t b 3 i n p 3 1 / a 9 p 4 2 / a 1 8 p 4 1 / a 1 7 p 4 0 / a 1 6 p 3 2 / a 1 0 p 3 3 / a 1 1 p 3 4 / a 1 2 p 3 5 / a 1 3 p 3 6 / a 1 4 p 3 7 / a 1 5 v c c p 4 3 / a 1 9 p 9 6 / a n e x 1 / s o u t 4 r e s e t p 8 5 / n m i p 8 4 / i n t 2 p 7 6 / t a 3 o u t p 7 5 / t a 2 i n p 7 4 / t a 2 o u t p 7 2 / c l k 2 / t a 1 o u t p 7 1 / r x d 2 / s c l / t a 0 i n / t b 5 i n p 7 3 / c t s 2 / r t s 2 / t a 1 i n p 5 3 / b c l k p 5 6 / a l e p 4 4 / c s 0 p 4 6 / c s 2 p 4 7 / c s 3 p 5 0 / w r l / w r p 5 1 / w r h / b h e p 5 2 / r d p 5 4 / h l d a p 5 5 / h o l d 1 0 8 1 0 7 1 0 6 1 0 5 1 0 4 1 0 3 1 0 2 1 0 1 1 0 0 9 9 9 8 9 7 9 6 9 5 9 4 9 3 9 2 9 1 9 0 8 9 8 8 8 7 8 6 8 5 8 4 8 3 8 2 8 1 8 0 7 9 7 8 7 7 7 6 7 5 7 4 7 3 7 1 7 0 6 9 6 8 6 7 6 6 6 5 6 4 6 3 6 2 6 1 6 0 5 9 7 2 p 0 7 / d 7 p 0 2 / d 2 p 0 3 / d 3 p 0 4 / d 4 p 0 5 / d 5 p 0 6 / d 6 p 0 0 / d 0 p 0 1 / d 1 1 1 0 1 1 1 1 1 2 1 1 3 1 1 4 1 1 5 1 1 6 1 0 9 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 m 3 0 6 h 2 m c - x x x f p p 8 3 / i n t 1 p 8 2 / i n t 0 p 6 1 / c l k 0 p 6 2 / r x d 0 p 6 3 / t x d 0 p 6 5 / c l k 1 p 6 6 / r x d 1 p 6 7 / t x d 1 v r e f a v s s p 5 7 / r d y / c l k o u t p 6 0 / c t s 0 / r t s 0 p 6 4 / c t s 1 / r t s 1 / c l k s 1 5 8 5 7 5 6 5 5 5 4 5 3 5 2 5 1 5 0 4 9 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 p 1 1 / s l i c e o n m 1 m 2 v s s 1 v d d 1 p 2 0 / a 0 ( / d 0 / - ) p 2 7 / a 7 ( / d 7 / d 6 ) p 3 0 / a 8 ( / - / d 7 ) p 2 6 / a 6 ( / d 6 / d 5 ) p 2 5 / a 5 ( / d 5 / d 4 ) p 2 4 / a 4 ( / d 4 / d 3 ) p 2 3 / a 3 ( / d 3 / d 2 ) p 2 2 / a 2 ( / d 2 / d 1 ) p 2 1 / a 1 ( / d 1 / d 0 ) p 1 4 / d 1 2 p 1 3 / d 1 1 p 1 2 / d 1 0 p 1 1 / d 9 v s s p 1 5 / d 1 3 / i n t 3 p 1 6 / d 1 4 / i n t 4 p 1 7 / d 1 5 / i n t 5 p 7 0 / t x d 2 / s d a / t a 0 o u t v s s 2 l p 2 l p 4 l p 3 v d d 2 p 1 0 / d 8 p 1 0 3 / a n 3 p 1 0 2 / a n 2 p 1 0 1 / a n 1 p 1 0 0 / a n 0 a v c c s y n c i n c v i n 1 v d d 3 v s s 3 f s c i n p 9 7 / a d t r g / s i n 4 p 4 5 / c s 1 p 1 0 7 / a n 7 / k i 3 p 1 0 4 / a n 4 / k i 0 p 1 0 5 / a n 5 / k i 1 p 1 0 6 / a n 6 / k i 2 s v r e f 1.3 pin configuration figures 1.3.1 shows the pin configuration (top view). 116p6a-a figure 1.3.1 pin configuration (top view)
4 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP 8 p o r t p 1 0 i / o p o r t s p o r t p 0 8 p o r t p 1 8 p o r t p 2 8 p o r t p 3 8 p o r t p 4 8 p o r t p 5 8 p o r t p 6 8 8 7 8 p o r t p 9 p o r t p 8 p o r t p 7 p o r t p 8 5 t i m e r t i m e r t a 0 ( 1 6 b i t s ) t i m e r t a 1 ( 1 6 b i t s ) t i m e r t a 2 ( 1 6 b i t s ) t i m e r t a 3 ( 1 6 b i t s ) t i m e r t a 4 ( 1 6 b i t s ) t i m e r t b 0 ( 1 6 b i t s ) t i m e r t b 1 ( 1 6 b i t s ) t i m e r t b 2 ( 1 6 b i t s ) t i m e r t b 3 ( 1 6 b i t s ) t i m e r t b 4 ( 1 6 b i t s ) t i m e r t b 5 ( 1 6 b i t s ) i n t e r n a l p e r i p h e r a l f u n c t i o n s w a t c h d o g t i m e r ( 1 5 b i t s ) d m a c ( 2 c h a n n e l s ) d - a c o n v e r t e r ( 8 b i t s x 2 c h a n n e l s ) a - d c o n v e r t e r ( 8 b i t s x 8 c h a n n e l s e x p a n d a b l e u p t o 1 0 c h a n n e l s ) u a r t / c l o c k s y n c h r o n o u s s i / o ( 8 b i t s x 3 c h a n n e l s ) s y s t e m c l o c k g e n e r a t o r x i n - x o u t x c i n - x c o u t m 1 6 c / 6 0 s e r i e s 1 6 - b i t c p u c o r e r 0 l r 0 h r 1 hr 1 l r 2 r 3 a 0 a 1 f b r 0 l r 0 h r 1 hr 1 l r 2 r 3 a 0 a 1 f b r e g i s t e r s i s p u s p s t a c k p o i n t e r v e c t o r t a b l e i n t b c r c a r i t h m e t i c c i r c u i t ( c c i t t ) ( p o l y n o m i a l : x 1 6 + x 1 2 + x 5 + 1 ) m u l t i p l i e r m e m o r y r o m ( 1 2 8 k b y t e s ) s b f l g p c p r o g r a m c o u n t e r c l o c k s y n c h r o n o u s s i / o ( 8 b i t s x 2 c h a n n e l s ) d a t a a c q u i s i t i o n c o n t r o l l e r p o r t p 1 1 f l a g r e g i s t e r r a m ( 5 k b y t e s ) 1.4 block diagram figure 1.4.1 is a block diagram of the M306H2MC-XXXFP. figure 1.4.1 block diagram of M306H2MC-XXXFP
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 5 rev. 1.0 M306H2MC-XXXFP table 1.5.1 performance outline of M306H2MC-XXXFP 1.5 performance outline table 1.5.1 is a performance outline of M306H2MC-XXXFP. item performance number of basic instructions 91 instructions shortest instruction execution time 100ns (f(x in )=10mh z ) memory rom 128k bytes capacity ram 5k bytes i/o port p0 to p10 (except p8 5 ) 8 bits ? ? ? ? ? ? ? ? ? ? ?
6 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP table 1.5.2 pin description b y t e e x t e r n a l d a t a b u s w i d t h s e l e c t i n p u t t h i s p i n s e l e c t s t h e w i d t h o f a n e x t e r n a l d a t a b u s . a 1 6 - b i t w i d t h i s s e l e c t e d w h e n t h i s i n p u t i s l ; a n 8 - b i t w i d t h i s s e l e c t e d w h e n t h i s i n p u t i s h . t h i s i n p u t m u s t b e f i x e d t o e i t h e r h o r l . c o n n e c t t h i s p i n t o t h e v s s p i n w h e n n o t u s i n g e x t e r n a l d a t a b u s . i n p u t v c c , v s s c n v s s s i g n a l n a m e p o w e r s u p p l y i n p u t c n v s s s u p p l y 4 . 7 5 t o 5 . 2 5 v t o t h e v c c p i n . s u p p l y 0 v t o t h e v s s p i n . f u n c t i o n t h i s p i n s w i t c h e s b e t w e e n p r o c e s s o r m o d e s . c o n n e c t t h i s p i n t o t h e v s s p i n w h e n a f t e r a r e s e t y o u w a n t t o s t a r t o p e r a t i o n i n s i g n a l - c h i p m o d e ( m e m o r y e x p a n s i o n m o d e ) o r t h e v c c p i n w h e n s t a r t i n g o p e r a t i o n i n m i c r o p r o c e s s o r m o d e . p i n n a m e i n p u t i / o t y p e a v c c a n a l o g p o w e r s u p p l y i n p u t t h i s p i n i s a p o w e r s u p p l y i n p u t f o r t h e a - d c o n v e r t e r . c o n n e c t t h i s p i n t o v c c . x i n x o u t c l o c k i n p u t c l o c k o u t p u t t h e s e p i n s a r e p r o v i d e d f o r t h e m a i n c l o c k g e n e r a t i n g c i r c u i t . c o n n e c t a c e r a m i c r e s o n a t o r o r c r y s t a l b e t w e e n t h e x i n a n d t h e x o u t p i n s . to u s e a n e x t e r n a l l y d e r i v e d c l o c k , i n p u t i t t o t h e x i n p i n a n d l e a v e t h e x o u t p i n o p e n . i n p u t o u t p u t v r e f r e f e r e n c e v o l t a g e i n p u t t h i s p i n i s a r e f e r e n c e v o l t a g e i n p u t f o r t h e a - d c o n v e r t e r . i n p u t p 0 0 t o p 0 7 i / o p o r t p 0 t h i s i s a n 8 - b i t c m o s i / o p o r t . i t h a s a n i n p u t / o u t p u t p o r t d i r e c t i o n r e g i s t e r t h a t a l l o w s t h e u s e r t o s e t e a c h p i n f o r i n p u t o r o u t p u t i n d i v i d u a l l y . w h e n u s e d f o r i n p u t i n s i g n a l - c h i p m o d e , t h e p o r t c a n b e s e t t o h a v e o r n o t h a v e a p u l l - u p r e s i s t o r i n u n i t s o f f o u r b i t s b y s o f t w a r e . i n m e m o r y e x p a n s i o n a n d m i c r o p r o c e s s o r m o d e s , s e l e c t i o n o f t h e i n t e r n a l p u l l - r e s i s t o r i n n o t a v a i l a b l e i n p u t / o u t p u t a v s s t h i s p i n i s a p o w e r s u p p l y i n p u t f o r t h e a - d c o n v e r t e r . c o n n e c t t h i s p i n t o v s s . a n a l o g p o w e r s u p p l y i n p u t r e s e t i n p u t a l o n t h i s i n p u t r e s e t s t h e m i c r o c o m p u t e r . i n p u t r e s e t p 1 0 t o p 1 7 i / o p o r t p 1 t h i s i s a n 8 - b i t i / o p o r t e q u i v a l e n t t o p 0 . p i n s i n t h i s p o r t a l s o f u n c t i o n a s e x t e r n a l i n t e r r u p t p i n s a s s e l e c t e d b y s o f t w a r e . i n p u t / o u t p u t d 0 t o d 7 w h e n s e t a s a s e p a r a t e b u s , t h e s e p i n s i n p u t a n d o u t p u t d a t a ( d 0 d 7 ) . i n p u t / o u t p u t d 8 t o d 1 5 w h e n s e t a s a s e p a r a t e b u s , t h e s e p i n s i n p u t a n d o u t p u t d a t a ( d 8 d 1 5 ) . i n p u t / o u t p u t p 2 0 t o p 2 7 i / o p o r t p 2 t h i s i s a n 8 - b i t i / o p o r t e q u i v a l e n t t o p 0 . i n p u t / o u t p u t a 0 t o a 7 t h e s e p i n s o u t p u t 8 l o w - o r d e r a d d r e s s b i t s ( a 0 a 7 ) . o u t p u t a 0 / d 0 t o a 7 / d 7 i f t h e e x t e r n a l b u s i s s e t a s a n 8 - b i t w i d e m u l t i p l e x e d b u s , t h e s e p i n s i n p u t a n d o u t p u t d a t a ( d 0 d 7 ) a n d o u t p u t 8 l o w - o r d e r a d d r e s s b i t s ( a 0 a 7 ) s e p a r a t e d i n t i m e b y m u l t i p l e x i n g . i n p u t / o u t p u t a 0 , a 1 / d 0 t o a 7 / d 6 i f t h e e x t e r n a l b u s i s s e t a s a 1 6 - b i t w i d e m u l t i p l e x e d b u s , t h e s e p i n s i n p u t a n d o u t p u t d a t a ( d 0 d 6 ) a n d o u t p u t a d d r e s s ( a 1 a 7 ) s e p a r a t e d i n t i m e b y m u l t i p l e x i n g . t h e y a l s o o u t p u t a d d r e s s ( a 0 ) . o u t p u t i n p u t / o u t p u t p 3 0 t o p 3 7 i / o p o r t p 3 t h i s i s a n 8 - b i t i / o p o r t e q u i v a l e n t t o p 0 . i n p u t / o u t p u t a 8 t o a 1 5 t h e s e p i n s o u t p u t 8 m i d d l e - o r d e r a d d r e s s b i t s ( a 8 a 1 5 ) . o u t p u t a 8 / d 7 , a 9 t o a 1 5 i f t h e e x t e r n a l b u s i s s e t a s a 1 6 - b i t w i d e m u l t i p l e x e d b u s , t h e s e p i n s i n p u t a n d o u t p u t d a t a ( d 7 ) a n d o u t p u t a d d r e s s ( a 8 ) s e p a r a t e d i n t i m e b y m u l t i p l e x i n g . t h e y a l s o o u t p u t a d d r e s s ( a 9 a 1 5 ) . i n p u t / o u t p u t o u t p u t p 4 0 t o p 4 7 i / o p o r t p 4 t h i s i s a n 8 - b i t i / o p o r t e q u i v a l e n t t o p 0 . i n p u t / o u t p u t o u t p u t o u t p u t c s 0 t o c s 3 , a 1 6 t o a 1 9 t h e s e p i n s o u t p u t c s 0 ? s 3 s i g n a l s a n d a 1 6 a 1 9 . c s 0 ? s 3 a r e c h i p s e l e c t s i g n a l s u s e d t o s p e c i f y a n a c c e s s s p a c e . a 1 6 a 1 9 a r e 4 h i g h - o r d e r a d d r e s s b i t s .
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 7 rev. 1.0 M306H2MC-XXXFP table 1.5.3 pin description s i g n a l n a m ef u n c t i o n p i n n a m ei / o t y p e i / o p o r t p 5i n p u t / o u t p u t i n p u t / o u t p u t i n p u t / o u t p u t i n p u t / o u t p u t i n p u t / o u t p u t i n p u t / o u t p u t i n p u t i n p u t / o u t p u t i n p u t / o u t p u t i / o p o r t p 6 i / o p o r t p 7 i / o p o r t p 8 i / o p o r t p 8 5 i / o p o r t p 9 i / o p o r t p 1 0 p 5 0 t o p 5 7 p 6 0 t o p 6 7 p 7 0 t o p 7 7 p 8 0 t o p 8 4 , p 8 6 , p 8 7 , p 8 5 p 9 0 t o p 9 7 p 1 0 0 t o p 1 0 7 t h i s i s a n 8 - b i t i / o p o r t e q u i v a l e n t t o p 0 . i n s i n g l e - c h i p m o d e , p 5 7 i n t h i s p o r t o u t p u t s a d i v i d e - b y - 8 o r d i v i d e - b y - 3 2 c l o c k o f x i n o r a c l o c k o f t h e s a m e f r e q u e n c y a s x ci n a s s e l e c t e d b y s o f t w a r e . o u t p u t o u t p u t o u t p u t o u t p u t o u t p u t i n p u t o u t p u t i n p u t t h i s i s a n 8 - b i t i / o p o r t e q u i v a l e n t t o p 0 . w h e n u s e d i n p u t i n s i n g l e c h i p , m e m o r y e x p a n s i o n , a n d m i c r o p r o c e s s o r m o d e s , t h e p o r t c a n b e s e t t o h a v e o r n o t h a v e a p u l l - u p r e s i s t o r i n u n i t s o f f o u r b i t s b y s o f t w a r e . p i n s i n t h i s p o r t a l s o f u n c t i o n a s u a r t 0 a n d u a r t 1 i / o p i n s a s s e l e c t e d b y s o f t w a r e . t h i s i s a n 8 - b i t i / o p o r t e q u i v a l e n t t o p 6 ( p 7 0 a n d p 7 1 a r e n c h a n n e l o p e n - d r a i n o u t p u t ) . p i n s i n t h i s p o r t a l s o f u n c t i o n a s t i m e r a 0 a 3 , t i m e r b 5 o r u a r t 2 i / o p i n s a s s e l e c t e d b y s o f t w a r e . t h i s i s a n 8 - b i t i / o p o r t e q u i v a l e n t t o p 6 . p i n s i n t h i s p o r t a l s o f u n c t i o n a s s i / o 3 , 4 i / o p i n s , t i m e r b 0 b 4 i n p u t p i n s , d - a c o n v e r t e r o u t p u t p i n s , a - d c o n v e r t e r e x t e n d e d i n p u t p i n s , o r a - d t r i g g e r i n p u t p i n s a s s e l e c t e d b y s o f t w a r e . t h i s i s a n 8 - b i t i / o p o r t e q u i v a l e n t t o p 6 . p i n s i n t h i s p o r t a l s o f u n c t i o n a s a - d c o n v e r t e r i n p u t p i n s . f u r t h e r m o r e , p 1 0 4 p 1 0 7 a l s o f u n c t i o n a s i n p u t p i n s f o r t h e k e y i n p u t i n t e r r u p t f u n c t i o n . w r l / w r , w r h / b h e , r d , b c l k , h l d a , h o l d , a l e , r d y o u t p u t w r l , w r h ( w r a n d b h e ) , r d , b c l k , h l d a , a n d a l e s i g n a l s . w r l a n d w r h , a n d b h e a n d w r c a n b e s w i t c h e d u s i n g s o f t w a r e c o n t r o l . w r l , w r h , a n d r d s e l e c t e d w i t h a 1 6 - b i t e x t e r n a l d a t a b u s , d a t a i s w r i t t e n t o e v e n a d d r e s s e s w h e n t h e w r l s i g n a l i s l a n d t o t h e o d d a d d r e s s e s w h e n t h e w r h s i g n a l i s l . d a t a i s r e a d w h e n r d i s l . w r , b h e , a n d r d s e l e c t e d d a t a i s w r i t t e n w h e n w r i s l . d a t a i s r e a d w h e n r d i s l . o d d a d d r e s s e s a r e a c c e s s e d w h e n b h e i s l . u s e t h i s m o d e w h e n u s i n g a n 8 - b i t e x t e r n a l d a t a b u s . w h i l e t h e i n p u t l e v e l a t t h e h o l d p i n i s l , t h e m i c r o c o m p u t e r i s p l a c e d i n t h e h o l d s t a t e . w h i l e i n t h e h o l d s t a t e , h l d a o u t p u t s a l l e v e l . a l e i s u s e d t o l a t c h t h e a d d r e s s . w h i l e t h e i n p u t l e v e l o f t h e r d y p i n i s l , t h e m i c r o c o m p u t e r i s i n t h e r e a d y s t a t e . p 8 0 t o p 8 4 , p 8 6 , a n d p 8 7 a r e i / o p o r t s w i t h t h e s a m e f u n c t i o n s a s p 6 . u s i n g s o f t w a r e , t h e y c a n b e m a d e t o f u n c t i o n a s t h e i / o p i n s f o r t i m e r a 4 a n d t h e i n p u t p i n s f o r e x t e r n a l i n t e r r u p t s . p 8 6 a n d p 8 7 c a n b e s e t u s i n g s o f t w a r e t o f u n c t i o n a s t h e i / o p i n s f o r a s u b c l o c k g e n e r a t i o n c i r c u i t . i n t h i s c a s e , c o n n e c t a q u a r t z o s c i l l a t o r b e t w e e n p 8 6 ( x c o u t p i n ) a n d p 8 7 ( x c i n p i n ) . p 8 5 i s a n i n p u t - o n l y p o r t t h a t a l s o f u n c t i o n s f o r n m i . t h e n m i i n t e r r u p t i s g e n e r a t e d w h e n t h e i n p u t a t t h i s p i n c h a n g e s f r o m h t o l . t h e n m i f u n c t i o n c a n n o t b e c a n c e l l e d u s i n g s o f t w a r e . t h e p u l l - u p c a n n o t b e s e t f o r t h i s p i n . o u t p u t p o r t p 1 1 p 1 1o u t p u t t h i s i s a 1 - b i t o u t p u t - o n l y p o r t . p i n s i n t h i s p o r t a l s o f u n c t i o n a s s l i c e o n o u t p u t p i n s a s s e l e c t e d b y s o f t w a r e .
8 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP table 1.5.4 pin description signal name function pin name i/o type synchronous slice level input svref input when slice the vertical synchronous signal, input slice power. composite video signal input 1 cvin1 input this pin inputs the external composite video signal. data slices this signal internally by setting. composite video signal input 2 syncin input test input 1 m1 input this is an input pin for test. supply 0 v to the pin. filter output 1 lp2 output this is a filter output pin 1 (for f sc ). filter output 2 lp3 output this is a filter output pin 2 (for vps). fsc input pin for synchronous signal generation fscin input sub-carrier (fsc) input pin for synchronous signal generation. filter output 3 lp4 output this is a filter output pin 3 (for pdc). this pin inputs the external composite video signal. synchronous devides this signal internally. power supply input v dd 1, v ss 1 digital power supply pin. supply 4.75 to 5.25 v to the v dd 1 pin. supply 0 v to the v ss 1 pin. power supply input v dd 2, v ss 2 analog power supply pin. supply 4.75 to 5.25 v to the v dd 2 pin. supply 0 v to the v ss 2 pin power supply input v dd 3, v ss 3 analog power supply pin. supply 4.75 to 5.25 v to the v dd 3 pin. supply 0 v to the v ss 3 pin test input 2 m2 input this is an input pin for test. supply 0 v to the pin.
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 9 rev. 1.0 M306H2MC-XXXFP 2. operation of functional bloks the M306H2MC-XXXFP accommodates certain units in a single chip. these units include ram to store instructions and data and the central processing unit (cpu) to execute arithmetic/logic operations. also included are peripheral units such as timers, serial i/o, d-a converter, dmac, crc calculation circuit, a-d converter, data slicer circuit and i/o ports. the following explains each unit. 2.1 memory figure 2.1.1 is a memory map of the M306H2MC-XXXFP. the address space extends the 1m bytes from address 00000 16 to fffff 16 . from address fffff 16 down is rom. in the M306H2MC-XXXFP, can use from address from e0000 16 to fffff 16 as 128k bytes internal rom area. the vector table for fixed _______ interrupts such as the reset and nmi are mapped to from address fffdc 16 to fffff 16 . the starting address of the interrupt routine is stored here. the address of the vector table for timer interrupts, etc., can be set as desired using the internal register (intb). see the section on interrupts for details. 5k bytes of internal ram is mapped to from address 00400 16 to 017ff 16 . in addition to storing data, the ram also stores the stack used when calling subroutines and when interrupts are generated. the sfr area is mapped to from address 00000 16 to 003ff 16 . this area accommodates the control registers for peripheral devices such as i/o ports, a-d converter, serial i/o, and timers, etc. figures 2.1.2 to 2.1.4 are location of peripheral unit control registers. any part of the sfr area that is not occupied is reserved and cannot be used for other purposes. the special page vector table is mapped to from address ffe00 16 to fffdb 16 . if the starting addresses of subroutines or the destination addresses of jumps are stored here, subroutine call instructions and jump instructions can be used as 2-byte instructions, reducing the number of program steps. in memory expansion mode and microprocessor mode, a part of the spaces are reserved and cannot be used. the following spaces cannot be used. ?the space between 01800 16 and 03fff 16 (memory expansion and microprocessor mode) ?the space between d0000 16 and dffff 16 (memory expansion mode) figure 2.1.1 memory map 0 0 0 0 0 1 6 f f f f f 1 6 0 0 4 0 0 1 6 0 4 0 0 0 1 6 0 1 7 f f 1 6 i n t e r n a l r o m a r e a s f r a r e a f o r d e t a i l s , s e e f i g u r e s 2 . 1 . 2 t o 2 . 1 . 4 i n t e r n a l r a m a r e a i n t e r n a l r e s e r v e d a r e a ( n o t e 1 ) ffe00 16 fffdc 16 fffff 16 u n d e f i n e d i n s t r u c t i o n o ver fl ow b r k i n s t r u c t i o n address match single step w a t c h d o g t i m e r r e s e t s p e c i a l p a g e v e c t o r t a b l e d b c n m i 0 1 8 0 0 1 6 0 3 f f f 1 6 i n t e r n a l r e s e r v e d a r e a ( n o t e 2 ) e 0 0 0 0 1 6 d 0 0 0 0 1 6 e x t e r n a l a r e a 0 0 3 f f 1 6 n o t e 1 : d u r i n g m e m o r y e x p a n s i o n a n d m i c r o p r o c e s s o r m o d e s , c a n n o t b e u s e d . 2 : i n m e m o r y e x p a n s i o n m o d e , c a n n o t b e u s e d .
10 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP figure 2.1.2 location of peripheral unit control registers (1) note: location in the sfr area where nothing is allocated are reserved. do not access these areas for read or write. 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 0010 16 0011 16 0012 16 0013 16 0014 16 0015 16 0016 16 0017 16 0018 16 0019 16 001a 16 001b 16 001c 16 001d 16 001e 16 001f 16 0020 16 0021 16 0022 16 0023 16 0024 16 0025 16 0026 16 0027 16 0028 16 0029 16 002a 16 002b 16 002c 16 002d 16 002e 16 002f 16 0030 16 0031 16 0032 16 0033 16 0034 16 0035 16 0036 16 0037 16 0038 16 0039 16 003a 16 003b 16 003c 16 003d 16 003e 16 003f 16 0040 16 0041 16 0042 16 0043 16 0044 16 0045 16 0046 16 0047 16 0048 16 0049 16 004a 16 004b 16 004c 16 004d 16 004e 16 004f 16 0050 16 0051 16 0052 16 0053 16 0054 16 0055 16 0056 16 0057 16 0058 16 0059 16 005a 16 005b 16 005c 16 005d 16 005e 16 005f 16 0060 16 0200 16 0201 16 0202 16 0203 16 0204 16 0205 16 0206 16 0207 16 0208 16 0209 16 020a 16 020b 16 020c 16 020d 16 020e 16 020f 16 0210 16 0211 16 0212 16 0213 16 0214 16 0215 16 0216 16 0217 16 0218 16 0219 16 021a 16 021b 16 021c 16 021d 16 021e 16 021f 16 0220 16 033f 16 dma0 control register (dm0con) dma0 source pointer (sar0) dma0 transfer counter (tcr0) dma1 control register (dm1con) dma1 source pointer (sar1) dma1 transfer counter (tcr1) dma1 destination pointer (dar1) watchdog timer start register (wdts) watchdog timer control register (wdc) processor mode register 0 (pm0) address match interrupt register 0 (rmad0) address match interrupt register 1 (rmad1) chip select control register (csr) system clock control register 0 (cm0) system clock control register 1 (cm1) address match interrupt enable register (aier) protect register (prcr) processor mode register 1(pm1) dma0 destination pointer (dar0) timer a1 interrupt control register (ta1ic) uart0 transmit interrupt control register (s0tic) timer a0 interrupt control register (ta0ic) timer a2 interrupt control register (ta2ic) uart0 receive interrupt control register (s0ric) uart1 transmit interrupt control register (s1tic) uart1 receive interrupt control register (s1ric) dma1 interrupt control register (dm1ic) dma0 interrupt control register (dm0ic) key input interrupt control register (kupic) a-d conversion interrupt control register (adic) bus collision detection interrupt control register (bcnic) uart2 transmit interrupt control register (s2tic) uart2 receive interrupt control register (s2ric) int1 interrupt control register (int1ic) timer b0 interrupt control register (tb0ic) timer b2 interrupt control register (tb2ic) timer a3 interrupt control register (ta3ic) int2 interrupt control register (int2ic) int0 interrupt control register (int0ic) timer b1 interrupt control register (tb1ic) timer a4 interrupt control register (ta4ic) int3 interrupt control register(int3ic) timer b5 interrupt control register (tb5ic) timer b4 interrupt control register (tb4ic) timer b3 interrupt control register (tb3ic) si/o4 interrupt control register (s4ic) int5 interrupt control register(int5ic) si/o3 interrupt control register (s3ic) int4 interrupt control register(int4ic) slice ram address control register slice ram data control register address control register for expansion register data control register for expansion register humming 8/4 register humming 24/18 register 0 humming 24/18 register 1
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 11 rev. 1.0 M306H2MC-XXXFP figure 2.1.3 location of peripheral unit control registers (2) 0380 16 0381 16 0382 16 0383 16 0384 16 0385 16 0386 16 0387 16 0388 16 0389 16 038a 16 038b 16 038c 16 038d 16 038e 16 038f 16 0390 16 0391 16 0392 16 0393 16 0394 16 0395 16 0396 16 0397 16 0398 16 0399 16 039a 16 039b 16 039c 16 039d 16 039e 16 039f 16 03a0 16 03a1 16 03a2 16 03a3 16 03a4 16 03a5 16 03a6 16 03a7 16 03a8 16 03a9 16 03aa 16 03ab 16 03ac 16 03ad 16 03ae 16 03af 16 03b0 16 03b1 16 03b2 16 03b3 16 03b4 16 03b5 16 03b6 16 03b7 16 03b8 16 03b9 16 03ba 16 03bb 16 03bc 16 03bd 16 03be 16 03bf 16 0340 16 0341 16 0342 16 0343 16 0344 16 0345 16 0346 16 0347 16 0348 16 0349 16 034a 16 034b 16 034c 16 034d 16 034e 16 034f 16 0350 16 0351 16 0352 16 0353 16 0354 16 0355 16 0356 16 0357 16 0358 16 0359 16 035a 16 035b 16 035c 16 035d 16 035e 16 035f 16 0360 16 0361 16 0362 16 0363 16 0364 16 0365 16 0366 16 0367 16 0368 16 0369 16 036a 16 036b 16 036c 16 036d 16 036e 16 036f 16 0370 16 0371 16 0372 16 0373 16 0374 16 0375 16 0376 16 0377 16 0378 16 0379 16 037a 16 037b 16 037c 16 037d 16 037e 16 037f 16 timer b3 register (tb3) timer b4 register (tb4) timer b5 register (tb5) timer b3, 4, 5 count start flag (tbsr) timer b3 mode register (tb3mr) timer b4 mode register (tb4mr) timer b5 mode register (tb5mr) interrupt cause select register (ifsr) timer a0 (ta0) timer a1 (ta1) timer a2 (ta2) timer b0 (tb0) timer b1 (tb1) timer b2 (tb2) count start flag (tabsr) one-shot start flag (onsf) timer a0 mode register (ta0mr) timer a1 mode register (ta1mr) timer a2 mode register (ta2mr) timer b0 mode register (tb0mr) timer b1 mode register (tb1mr) timer b2 mode register (tb2mr) up-down flag (udf) timer a3 (ta3) timer a4 (ta4) timer a3 mode register (ta3mr) timer a4 mode register (ta4mr) trigger select register (trgsr) clock prescaler reset flag (cpsrf) uart0 transmit/receive mode re g ister ( u0mr ) uart0 transmit buffer register (u0tb) uart0 receive buffer register (u0rb) uart1 transmit/receive mode re g ister ( u1mr ) uart1 transmit buffer register (u1tb) uart1 receive buffer register (u1rb) uart0 bit rate generator (u0brg) uart0 transmit/receive control re g ister 0 ( u0c0 ) uart0 transmit/receive control re g ister 1 ( u0c1 ) uart1 bit rate generator (u1brg) uart1 transmit/receive control re g ister 0 ( u1c0 ) uart1 transmit/receive control re g ister 1 ( u1c1 ) dma1 request cause select register (dm1sl) dma0 request cause select register (dm0sl) crc data register (crcd) crc input register (crcin) si/o3 transmit/receive register (s3trr) si/o4 transmit/receive register (s4trr) si/o3 control register (s3c) si/o3 bit rate generator (s3brg) si/o4 bit rate generator (s4brg) si/o4 control register (s4c) uart2 special mode register (u2smr) uart2 receive buffer re g ister ( u2rb ) uart2 transmit buffer re g ister ( u2tb ) uart2 transmit/receive control re g ister 0 ( u2c0 ) uart2 transmit/receive mode re g ister ( u2mr ) uart2 transmit/receive control re g ister 1 ( u2c1 ) uart2 bit rate g enerator ( u2brg ) uart transmit/receive control re g ister 2 ( ucon ) uart2 special mode register 2(u2smr2) uart2 special mode register 3(u2smr3) flash memory control register (fer) (note1) note 1: this register is only exist in flash memory version. note 2: locations in the sfr area where nothing is allocated are reserved areas. do not access these areas for read or write.
12 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP figure 2.1.4 location of peripheral unit control registers (3) 03c0 16 03c1 16 03c2 16 03c3 16 03c4 16 03c5 16 03c6 16 03c7 16 03c8 16 03c9 16 03ca 16 03cb 16 03cc 16 03cd 16 03ce 16 03cf 16 03d0 16 03d1 16 03d2 16 03d3 16 03d4 16 03d5 16 03d6 16 03d7 16 03d8 16 03d9 16 03da 16 03db 16 03dc 16 03dd 16 03de 16 03df 16 03e0 16 03e1 16 03e2 16 03e3 16 03e4 16 03e5 16 03e6 16 03e7 16 03e8 16 03e9 16 03ea 16 03eb 16 03ec 16 03ed 16 03ee 16 03ef 16 03f0 16 03f1 16 03f2 16 03f3 16 03f4 16 03f5 16 03f6 16 03f7 16 03f8 16 03f9 16 03fa 16 03fb 16 03fc 16 03fd 16 03fe 16 03ff 16 a-d register 7 (ad7) a-d register 0 (ad0) a-d register 1 (ad1) a-d register 2 (ad2) a-d register 3 (ad3) a-d register 4 (ad4) a-d register 5 (ad5) a-d register 6 (ad6) port p0 (p0) port p0 direction register (pd0) port p1 (p1) port p1 direction register (pd1) port p2 (p2) port p2 direction register (pd2) port p3 (p3) port p3 direction register (pd3) port p4 (p4) port p4 direction register (pd4) port p5 (p5) port p5 direction register (pd5) port p6 (p6) port p6 direction register (pd6) port p7 (p7) port p7 direction register (pd7) port p8 (p8) port p8 direction register (pd8) port p9 (p9) port p9 direction register (pd9) port p10 (p10) port p10 direction register (pd10) pull-up control register 0 (pur0) pull-up control register 1 (pur1) pull-up control register 2 (pur2) a-d control register 0 (adcon0) a-d control register 1 (adcon1) d-a register 0 (da0) d-a register 1 (da1) d-a control register (dacon) a-d control register 2 (adcon2) port control register (pcr) note: locations in the sfr area where nothing is allocated are reserved areas. do not access these areas for read or write.
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 13 rev. 1.0 M306H2MC-XXXFP 2.2 central processing unit (cpu) the cpu has 13 registers shown in figure 2.2.1. seven of these registers (r0, r1, r2, r3, a0, a1, and fb) come in two sets; therefore, these have two register banks. aaaaaaa aaaaaaa h l b15 b8 b7 b0 r0 (note) aaaaaaa h l b15 b8 b7 b0 r1 (note) r2 (note) aaaaaaa aaaaaaa b15 b0 r3 (note) aaaaaaa b15 b0 a0 (note) aaaaaaa aaaaaaa b15 b0 a1 (note) aaaaaaa aaaaaaa b15 b0 fb (note) aaaaaaa b15 b0 data registers address registers frame base registers b15 b0 b15 b0 b15 b0 b15 b0 b0 b19 b0 b19 h l program counter interrupt table register user stack pointer interrupt stack pointer static base register flag register pc intb usp isp sb flg note: these registers consist of two register banks. a a aa aa aa aa a a aaaaaaa aaaaaaa a a aa aa aa aa aa aa a a c d z s b o i u ipl figure 2.2.1 central processing unit register (1) data registers (r0, r0h, r0l, r1, r1h, r1l, r2, and r3) data registers (r0, r1, r2, and r3) are configured with 16 bits, and are used primarily for transfer and arithmetic/logic operations. registers r0 and r1 each can be used as separate 8-bit data registers, high-order bits as (r0h/r1h), and low-order bits as (r0l/r1l). in some instructions, registers r2 and r0, as well as r3 and r1 can use as 32-bit data registers (r2r0/r3r1). (2) address registers (a0 and a1) address registers (a0 and a1) are configured with 16 bits, and have functions equivalent to those of data registers. these registers can also be used for address register indirect addressing and address register relative addressing. in some instructions, registers a1 and a0 can be combined for use as a 32-bit address register (a1a0).
14 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP (3) frame base register (fb) frame base register (fb) is configured with 16 bits, and is used for fb relative addressing. (4) program counter (pc) program counter (pc) is configured with 20 bits, indicating the address of an instruction to be executed. (5) interrupt table register (intb) interrupt table register (intb) is configured with 20 bits, indicating the start address of an interrupt vector table. (6) stack pointer (usp/isp) stack pointer comes in two types: user stack pointer (usp) and interrupt stack pointer (isp), each config- ured with 16 bits. your desired type of stack pointer (usp or isp) can be selected by a stack pointer select flag (u flag). this flag is located at the position of bit 7 in the flag register (flg). (7) static base register (sb) static base register (sb) is configured with 16 bits, and is used for sb relative addressing. (8) flag register (flg) flag register (flg) is configured with 11 bits, each bit is used as a flag. figure 2.2.2 shows the flag .register (flg). the following explains the function of each flag: ?bit 0: carry flag (c flag) this flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit. ?bit 1: debug flag (d flag) this flag enables a single-step interrupt. when this flag is ?? a single-step interrupt is generated after instruction execution. this flag is cleared to ?? when the interrupt is acknowledged. ?bit 2: zero flag (z flag) this flag is set to ??when an arithmetic operation resulted in 0; otherwise, cleared to ?? ?bit 3: sign flag (s flag) this flag is set to ?? when an arithmetic operation resulted in a negative value; otherwise, cleared to ? . ?bit 4: register bank select flag (b flag) this flag chooses a register bank. register bank 0 is selected when this flag is ??; register bank 1 is selected when this flag is ?? ?bit 5: overflow flag (o flag) this flag is set to ??when an arithmetic operation resulted in overflow; otherwise, cleared to ?? ?bit 6: interrupt enable flag (i flag) this flag enables a maskable interrupt. an interrupt is disabled when this flag is ?? and is enabled when this flag is ?? this flag is cleared to ??when the interrupt is acknowledged.
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 15 rev. 1.0 M306H2MC-XXXFP figure 2.2.2 flag register (flg) carry flag debug flag zero flag sign flag register bank select flag overflow flag interrupt enable flag stack pointer select flag reserved area processor interrupt priority level reserved area flag register (flg) aa aa aa aa a a aa aa aaaaaaa aaaaaaa aa aa aa aa aa aa a a aa aa c d z s b o i u ipl b0 b15 ?bit 7: stack pointer select flag (u flag) interrupt stack pointer (isp) is selected when this flag is 0 ; user stack pointer (usp) is selected when this flag is 1 . this flag is cleared to 0 when a hardware interrupt is acknowledged or an int instruction of software interrupt nos. 0 to 31 is executed. ?bits 8 to 11: reserved area ?bits 12 to 14: processor interrupt priority level (ipl) processor interrupt priority level (ipl) is configured with three bits, for specification of up to eight processor interrupt priority levels from level 0 to level 7. if a requested interrupt has priority greater than the processor interrupt priority level (ipl), the interrupt is enabled. ?bit 15: reserved area the c, z, s, and o flags are changed when instructions are executed. see the software manual for details.
16 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP reset v cc 0.95v reset v cc 0v 0v 5v 5v 4.75v figure 2.3.1 example reset circuit 2.3 reset there are two kinds of resets; hardware and software. in both cases, operation is the same after the reset. (see ?oftware reset?for details of software resets.) this section explains on hardware resets. when the supply voltage is in the range where operation is guaranteed, a reset is effected by holding the reset pin level ??(0.2v cc max.) for at least 20 cycles. when the reset pin level is then returned to the ? level while main clock is stable, the reset status is cancelled and program execution resumes from the address in the reset vector table. figure 2.3.1 shows the example reset circuit. figure 2.3.2 shows the reset sequence. figure 2.3.2 reset sequence bclk address microprocessor mode byte = h bclk 24cycles ffffc 16 ffffd 16 ffffe 16 content of reset vector x in reset rd wr cs0 rd wr cs0 address microprocessor mode byte = l ffffc 16 ffffe 16 content of reset vector more than 20 cycles are needed address single chip mode ffffc 16 ffffe 16 content of reset vector
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 17 rev. 1.0 M306H2MC-XXXFP ____________ table 2.3.1 shows the statuses of the other pins while the reset pin level is l . figures 2.3.3 and 2.3.4 show the internal status of the microcomputer immediately after the reset is cancelled. 2.3.1 software reset writing 1 to bit 3 of the processor mode register 0 (address 0004 16 ) applies a (software) reset to the microcomputer. a software reset has almost the same effect as a hardware reset. the contents of internal ram are preserved. status pin name p0 p1 p2, p3, p4 0 to p4 3 p4 4 p4 5 to p4 7 p5 0 p5 1 p5 2 p5 3 p5 4 p5 5 p5 6 p5 7 p6, p7, p8 0 to p8 4 , p8 6 , p8 7 , p9, p10 cnv ss = v cc byte = v cc input port (floating) bclk output data input (floating) address output (undefined) cs0 output ( h level is output) input port (floating) rdy input (floating) ale output ( l level is output) hold input (floating) hlda output (the output value depends on the input to the hold pin) rd output ( h level is output) bhe output (undefined) wr output ( h level is output) input port (floating) (pull-up resistor is on) output port byte = v ss data input (floating) data input (floating) address output (undefined) bclk output ale output ( l level is output) cs0 output ( h level is output) wr output ( h level is output) rd output ( h level is output) rdy input (floating) bhe output (undefined) hlda output (the output value depends on the input to the hold pin) hold input (floating) input port (floating) (pull-up resistor is on) input port (floating) output port input port output port input port output port cnv ss input port (floating) input port (floating) input port (floating) input port (floating) input port (floating) input port (floating) input port (floating) input port (floating) input port (floating) input port (floating) input port (floating) input port (floating) input port (floating) input port (floating) p11 output port cvin1, svref, syncin fscin lp2, lp3, lp4 input port output port ____________ table 2.3.1 pin status when reset pin level is ?
18 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP figure 2.3.3 device's internal status after a reset is cleared x : n o t h i n g i s m a p p e d t o t h i s b i t ? : u n d e f i n e d t h e c o n t e n t o f o t h e r r e g i s t e r s a n d r a m i s u n d e f i n e d w h e n t h e m i c r o c o m p u t e r i s r e s e t . t h e i n i t i a l v a l u e s m u s t t h e r e f o r e b e s e t . n o t e : w h e n t h e v c c l e v e l i s a p p l i e d t o t h e c n v s s p i n , i t i s 0 3 1 6 a t a r e s e t . ( 0 0 0 4 1 6 ) p r o c e s s o r m o d e r e g i s t e r 0 ( n o t e ) 0 0 1 6 ( 0 0 0 5 1 6 ) p r o c e s s o r m o d e r e g i s t e r 1 0 0 0 ( 0 0 0 6 1 6 ) s y s t e m c l o c k c o n t r o l r e g i s t e r 0 1 00 00 10 0 ( 0 0 0 7 1 6 ) s y s t e m c l o c k c o n t r o l r e g i s t e r 1 0 00 10 00 0 ( 0 0 0 8 1 6 ) c h i p s e l e c t c o n t r o l r e g i s t e r 0 00 00 01 0 ( 0 0 0 9 1 6 ) a d d r e s s m a t c h i n t e r r u p t e n a b l e r e g i s t e r 0 0 p r o t e c t r e g i s t e r( 0 0 0 a 1 6 ) 00 0 0 00 ( 0 0 0 f 1 6 ) w a t c h d o g t i m e r c o n t r o l r e g i s t e r0 0? 0 ???? ( 0 0 1 5 1 6 ) ( 0 0 1 6 1 6 ) 0 ( 0 0 1 4 1 6 ) a d d r e s s m a t c h i n t e r r u p t r e g i s t e r 1 0 0 1 6 0 0 1 6 0 0 0 ( 0 0 2 c 1 6 ) d m a 0 c o n t r o l r e g i s t e r 00000?00 ( 0 0 3 c 1 6 ) d m a 1 c o n t r o l r e g i s t e r 00000?00 ( 0 0 4 b 1 6 ) d m a 0 i n t e r r u p t c o n t r o l r e g i s t e r ? 0 0 0 ( 0 0 4 c 1 6 ) d m a 1 i n t e r r u p t c o n t r o l r e g i s t e r ? 0 0 0 ( 0 0 4 d 1 6 ) k e y i n p u t i n t e r r u p t c o n t r o l r e g i s t e r ? 0 0 0 ( 0 0 4 a 1 6 ) b u s c o l l i s i o n d e t e c t i o n i n t e r r u p t c o n t r o l r e g i s t e r 0 0 0 ? ( 0 0 1 0 1 6 ) a d d r e s s m a t c h i n t e r r u p t r e g i s t e r 0 ( 0 0 1 1 1 6 ) ( 0 0 1 2 1 6 ) 0 0 0 1 6 0 0 1 6 0 0 0 ( 0 0 4 4 1 6 ) i n t 3 i n t e r r u p t c o n t r o l r e g i s t e r 00?000 ( 0 0 4 5 1 6 ) t i m e r b 5 i n t e r r u p t c o n t r o l r e g i s t e r ?000 ( 0 0 4 6 1 6 ) t i m e r b 4 i n t e r r u p t c o n t r o l r e g i s t e r ?000 ( 0 0 4 7 1 6 ) t i m e r b 3 i n t e r r u p t c o n t r o l r e g i s t e r ?000 ( 0 0 4 8 1 6 ) s i / o 4 i n t e r r u p t c o n t r o l r e g i s t e r 00?000 ( 0 0 4 9 1 6 ) s i / o 3 i n t e r r u p t c o n t r o l r e g i s t e r 00?000 a - d c o n v e r s i o n i n t e r r u p t c o n t r o l r e g i s t e r u a r t 2 t r a n s m i t i n t e r r u p t c o n t r o l r e g i s t e r u a r t 2 r e c e i v e i n t e r r u p t c o n t r o l r e g i s t e r ( 0 0 4 e 1 6 ) ? 0 0 0 ( 0 0 4 f 1 6 ) ( 0 0 5 0 1 6 ) ? 0 0 0 ? 0 0 0 u a r t 0 t r a n s m i t i n t e r r u p t c o n t r o l r e g i s t e r u a r t 0 r e c e i v e i n t e r r u p t c o n t r o l r e g i s t e r ( 0 0 5 1 1 6 ) ( 0 0 5 2 1 6 ) ? 0 0 0 ? 0 0 0 u a r t 1 t r a n s m i t i n t e r r u p t c o n t r o l r e g i s t e r u a r t 1 r e c e i v e i n t e r r u p t c o n t r o l r e g i s t e r t i m e r a 0 i n t e r r u p t c o n t r o l r e g i s t e r t i m e r a 1 i n t e r r u p t c o n t r o l r e g i s t e r t i m e r a 2 i n t e r r u p t c o n t r o l r e g i s t e r t i m e r a 3 i n t e r r u p t c o n t r o l r e g i s t e r t i m e r a 4 i n t e r r u p t c o n t r o l r e g i s t e r ( 0 0 5 3 1 6 ) ( 0 0 5 4 1 6 ) ( 0 0 5 5 1 6 ) ( 0 0 5 6 1 6 ) ( 0 0 5 7 1 6 ) ( 0 0 5 8 1 6 ) ( 0 0 5 9 1 6 ) ? 0 0 0 ? 0 0 0 ? 0 0 0 ? 0 0 0 ? 0 0 0 ? 0 0 0 ? 0 0 0 t i m e r b 0 i n t e r r u p t c o n t r o l r e g i s t e r t i m e r b 1 i n t e r r u p t c o n t r o l r e g i s t e r t i m e r b 2 i n t e r r u p t c o n t r o l r e g i s t e r i n t 0 i n t e r r u p t c o n t r o l r e g i s t e r i n t 1 i n t e r r u p t c o n t r o l r e g i s t e r i n t 2 i n t e r r u p t c o n t r o l r e g i s t e r ( 0 0 5 a 1 6 ) ( 0 0 5 b 1 6 ) ( 0 0 5 c 1 6 ) ( 0 0 5 d 1 6 ) ( 0 0 5 e 1 6 ) ( 0 0 5 f 1 6 ) ? 0 0 0 ? 0 0 0 ? 0 0 0 ? 000 00 ? 000 00 ? 000 00 s l i c e r a m a d d r e s s c o n t r o l r e g i s t e r s l i c e r a m d a t a c o n t r o l r e g i s t e r ( 0 2 0 e 1 6 ) 0 0 1 6 ( 0 2 0 f 1 6 ) 0 0 1 6 ( 0 2 1 0 1 6 ) 0 0 1 6 ( 0 2 1 1 1 6 ) 0 0 1 6 t i m e r b 3 , 4 , 5 c o u n t s t a r t f l a g t i m e r b 3 m o d e r e g i s t e r t i m e r b 4 m o d e r e g i s t e r t i m e r b 5 m o d e r e g i s t e r i n t e r r u p t c a u s e s e l e c t r e g i s t e r u a r t 2 t r a n s m i t / r e c e i v e c o n t r o l r e g i s t e r 1 u a r t 2 t r a n s m i t / r e c e i v e c o n t r o l r e g i s t e r 0 u a r t 2 t r a n s m i t / r e c e i v e m o d e r e g i s t e r s i / o 4 c o n t r o l r e g i s t e r u a r t 2 s p e c i a l m o d e r e g i s t e r s i / o 3 c o n t r o l r e g i s t e r u a r t 2 s p e c i a l m o d e r e g i s t e r 2 a d d r e s s c o n t r o l r e g i s t e r f o r e x p a n s i o n r e g i s t e r d a t a c o n t r o l r e g i s t e r f o r e x p a n s i o n r e g i s t e r h u m m i n g 8 / 4 r e g i s t e r h u m m i n g 2 4 / 1 8 r e g i s t e r 0 0 0 1 6 ( 0 3 7 8 1 6 ) ( 0 3 7 d 1 6 ) ( 0 3 7 c 1 6 ) 0 0 1 6 000 00001 010 00000 ( 0 3 4 0 1 6 ) ( 0 3 5 b 1 6 ) ( 0 3 5 c 1 6 ) ( 0 3 5 d 1 6 ) ( 0 3 5 f 1 6 ) ( 0 3 6 6 1 6 ) ( 0 3 7 7 1 6 ) ( 0 3 6 2 1 6 ) 00? 0000 00? 0000 00? 0000 4 0 1 6 0 0 1 6 4 0 1 6 000 ( 0 3 7 6 1 6 ) 0 0 1 6 ( 0 2 1 6 1 6 ) 0 0 1 6 ( 0 2 1 7 1 6 ) 0 0 1 6 ( 0 2 1 8 1 6 ) 0 0 1 6 ( 0 2 1 9 1 6 ) 0 0 1 6 ( 0 2 1 a 1 6 ) 0 0 1 6 ( 0 2 1 b 1 6 ) 0 0 1 6 ( 0 2 1 c 1 6 ) 0 0 1 6 ( 0 2 1 d 1 6 ) 0 0 1 6 ( 0 2 1 e 1 6 ) 0 0 1 6 ( 0 2 1 f 1 6 ) 0 0 1 6 h u m m i n g 2 4 / 1 8 r e g i s t e r 1
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 19 rev. 1.0 M306H2MC-XXXFP (0383 16 ) trigger select flag (0384 16 ) up-down flag (0396 16 ) timer a0 mode register (0397 16 ) timer a1 mode register (0398 16 ) timer a2 mode register (039b 16 ) timer b0 mode register (039c 16 ) timer b1 mode register (039d 16 ) timer b2 mode register (0399 16 ) timer a3 mode register (039a 16 ) timer a4 mode register (0382 16 ) one-shot start flag 00 16 00 16 0 00 16 00 16 00 16 00 16 00 16 0? 0000 00? 0000 00? 0000 (03ac 16 ) uart1 transmit/receive control register 0 (03ad 16 ) uart1 transmit/receive control register 1 (03b0 16 ) uart transmit/receive control register 2 (03b8 16 ) dma0 cause select register (03ba 16 ) dma1 cause select register 0 (03a0 16 ) uart0 transmit/receive mode register (03a4 16 ) uart0 transmit/receive control register 0 (03a5 16 ) uart0 transmit/receive control register 1 00 16 000 1000 000 0010 0 0 (03a8 16 ) uart1 transmit/receive mode register 00 16 000 1000 000 0010 0 0 00000 0 00 16 00 16 (03d4 16 ) a-d control register 2 (03d6 16 ) a-d control register 0 (03d7 16 ) a-d control register 1 0 000 0??? 0 00 16 0 00 0000 count start flag (0380 16 ) 00 16 0 (0381 16 ) clock prescaler reset flag x : nothing is mapped to this bit ? : undefined the content of other registers and ram is undefined when the microcomputer is reset. the initial values must therefore be set. note: when the v cc level is applied to the cnv ss pin, it is 02 16 at a reset. (03e2 16 ) port p0 direction register (03e3 16 ) port p1 direction register (03e6 16 ) port p2 direction register (03e7 16 ) port p3 direction register (03ea 16 ) port p4 direction register (03eb 16 ) port p5 direction register (03ee 16 ) port p6 direction register (03ef 16 ) port p7 direction register (03f2 16 ) port p8 direction register (03f3 16 ) port p9 direction register (03f6 16 ) port p10 direction register (03fc 16 ) pull-up control register 0 (03fd 16 ) pull-up control register 1(note) (03fe 16 ) pull-up control register 2 port control register 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 0 0 000 (03dc 16 ) d-a control register 00 16 frame base register (fb) address registers (a0/a1) interrupt table register (intb) user stack pointer (usp) interrupt stack pointer (isp) static base register (sb) flag register (flg) 0000 16 0000 16 00000 16 0000 16 0000 16 0000 16 0000 16 data registers (r0/r1/r2/r3) 0000 16 (03ff 16 ) 0000 figure 2.3.4 device's internal status after a reset is cleared
20 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP 2.4 processor mode (1) types of processor mode processor mode can be used at microprocessor mode. one of three processor modes can be selected:single-chip mode,memory expansion mode,and mi- cro-processor mode.the functions of some pins,the memory map,and the access space differ accord- ing to the selected processor mode. ?single-chip mode in single-chip mode,only internal memory space (sfr,internal ram,and internal rom)can be accessed.ports p0 to p10 can be used as programmable i/o ports or as i/o ports for the internal peripheral functions. ?memory expansion mode in memory expansion mode,external memory can be accessed in addition to the internal memory space (sfr,internal ram,and internal rom). in this mode,some of the pins function as the address bus,the data bus,and as control signals.the number of pins assigned to these functions depends on the bus and register settings.(see "bus settings " for details..) ?microprocessor mode in microprocessor mode,the sfr,internal ram,and external memory space can be accessed.the internal rom area cannot be accessed. in this mode,some of the pins function as the address bus,the data bus,and as control signals.the number of pins assigned to these functions depends on the bus and register settings.(see "2.4.1 bus settings " for details..) (2) setting processor modes the processor mode is set using the cnv ss pin and the processor mode bits (bits 1 and 0 at address 000416).do not set the processor mode bits to "10 2 ". regardless of the level of the cnv ss pin,changing the processor mode bits selects the mode.therefore, never change the processor mode bits when changing the contents of other bits.also do not attempt to shift to or from the microprocessor mode within the program stored in the internal rom area. ?applying vss to cnvss pin the microcomputer begins operation in single-chip mode after being reset.memory expansion mode is selected by writing "01 2 " to the processor mode is selected bits.. ?applying vcc to cnvss pin the microcomputer starts to operate in microprocessor mode after being reset. figure 2.4.1 shows the processor mode register 0 and 1. figure 2.4.2 shows the memory maps applicable for each of the modes when memory area dose not be expanded (normal mode).
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 21 rev. 1.0 M306H2MC-XXXFP p r o c e s s o r m o d e r e g i s t e r 0 ( n o t e 1 ) s y m b o la d d r e s sw h e n r e s e t p m 00 0 0 4 1 6 0 0 1 6 ( n o t e 2 ) b i t n a m ef u n c t i o n b i t s y m b o l w r b 7b 6b 5b 4b 3b 2b 1b 0 0 0 : s i n g l e - c h i p m o d e 0 1 : m e m o r y e x p a n s i o n m o d e 1 0 : i n h i b i t e d 1 1 : m i c r o p r o c e s s o r m o d e b 1 b 0 p m 0 3 p m 0 1 p m 0 0 p r o c e s s o r m o d e b i t p m 0 2 r / w m o d e s e l e c t b i t 0 : r d , b h e , w r 1 : r d , w r h , w r l s o f t w a r e r e s e t b i t t h e d e v i c e i s r e s e t w h e n t h i s b i t i s s e t t o 1 . t h e v a l u e o f t h i s b i t i s 0 w h e n r e a d . p m 0 4 0 0 : m u l t i p l e x e d b u s i s n o t u s e d 0 1 : a l l o c a t e d t o c s 2 s p a c e 1 0 : a l l o c a t e d t o c s 1 s p a c e 1 1 : a l l o c a t e d t o e n t i r e s p a c e ( n o t e 4 ) b 5 b 4 m u l t i p l e x e d b u s s p a c e s e l e c t b i t p m 0 5 p m 0 6 p m 0 7 p o r t p 4 0 t o p 4 3 f u n c t i o n s e l e c t b i t ( n o t e 3 ) 0 : a d d r e s s o u t p u t 1 : p o r t f u n c t i o n ( a d d r e s s i s n o t o u t p u t ) b c l k o u t p u t d i s a b l e b i t 0 : b c l k i s o u t p u t 1 : b c l k i s n o t o u t p u t ( p i n i s l e f t f l o a t i n g ) n o t e s 1 : s e t b i t 1 o f t h e p r o t e c t r e g i s t e r ( a d d r e s s 0 0 0 a 1 6 ) t o 1 w h e n w r i t i n g n e w v a l u e s t o t h i s r e g i s t e r . 2 : i f t h e v c c v o l t a g e i s a p p l i e d t o t h e c n v s s , t h e v a l u e o f t h i s r e g i s t e r w h e n r e s e t i s 0 3 1 6 . ( p m 0 0 a n d p m 0 1 b o t h a r e s e t t o 1 . ) 3 : v a l i d i n m i c r o p r o c e s s o r a n d m e m o r y e x p a n s i o n m o d e s . 4 : i f t h e e n t i r e s p a c e i s o f m u l t i p l e x e d b u s i n m e m o r y e x p a n s i o n m o d e , c h o s e a n 8 - b i t w i d t h . t h e p r o c e s s o r o p e r a t e s u s i n g t h e s e p a r a t e b u s a f t e r r e s e t i s r e v o k e d , s o t h e e n t i r e s p a c e m u l t i p l e x e d b u s c a n n o t b e c h o s e n i n m i c r o p r o c e s s o r m o d e . t h e h i g h e r - o r d e r a d d r e s s b e c o m e s a p o r t i f t h e e n t i r e s p a c e m u l t i p l e x e d b u s i s c h o s e n , s o o n l y 2 5 6 b y t e s c a n b e i n u s e d i n e a c h c h i p s e l e c t . p r o c e s s o r m o d e r e g i s t e r 1 ( n o t e ) s y m b o la d d r e s sw h e n r e s e t p m 10 0 0 5 1 6 0 0 0 0 0 x x 0 2 b i t n a m ef u n c t i o n b i t s y m b o l w r b 7b 6b 5b 4b 3b 2b 1b 0 n o t h i n g i s a s s i g n e d . i n a n a t t e m p t t o w r i t e t o t h e s e b i t s , w r i t e 0 . t h e v a l u e , i f r e a d , t u r n s o u t t o b e i n d e t e r m i n a t e . r e s e r v e d b i t m u s t a l w a y s b e s e t t o 0 0 0 0 n o t e : s e t b i t 1 o f t h e p r o t e c t r e g i s t e r ( a d d r e s s 0 0 0 a 1 6 ) t o 1 w h e n w r i t i n g n e w v a l u e s t o t h i s r e g i s t e r . p m 1 7w a i t b i t 0 : n o w a i t s t a t e 1 : w a i t s t a t e i n s e r t e d r e s e r v e d b i tm u s t a l w a y s b e s e t t o 0 00 r e s e r v e d b i tm u s t a l w a y s b e s e t t o 0 figure 2.4.1 processor mode registers
22 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP figure 2.4.2 memory maps in each processor mode s f r a r e a i n t e r n a l r a m a r e a i n h i b i t e d 0 0 0 0 0 1 6 0 0 4 0 0 1 6 0 1 7 f f 1 6 f f f f f 1 6 e x t e r n a l a r e a : a c c e s s i n g t h i s a r e a a l l o w s t h e u s e r t o a c c e s s a d e v i c e c o n n e c t e d e x t e r n a l l y t o t h e m i c r o c o m p u t e r . 0 4 0 0 0 1 6 i n t e r n a l r o m a r e a d 0 0 0 0 1 6 e 0 0 0 0 1 6 s f r a r e a i n t e r n a l r a m a r e a e x t e r n a l a r e a i n t e r n a l l y r e s e r v e d a r e a i n t e r n a l r o m a r e a i n t e r n a l l y r e s e r v e d a r e a s f r a r e a i n t e r n a l r a m a r e a e x t e r n a l a r e a i n t e r n a l l y r e s e r v e d a r e a s i n g l e - c h i p m o d em e m o r y e x p a n s i o n m o d em i c r o p r o c e s s o r m o d e
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 23 rev. 1.0 M306H2MC-XXXFP bus setting switching factor switching external address bus width bit 6 of processor mode register 0 switching external data bus width byte pin switching between separate and multiplex bus bits 4 and 5 of processor mode register 0 table 2.4.1 factors for switching bus settings (1) selecting external address bus width the address bus width for external output in the 1m bytes of address space can be set to 16 bits (64k bytes address space) or 20 bits (1m bytes address space). when bit 6 of the processor mode register 0 is set to 1 , the external address bus width is set to 16 bits, and p2 and p3 become part of the address bus. p4 0 to p4 3 can be used as programmable i/o ports. when bit 6 of processor mode register 0 is set to 0 , the external address bus width is set to 20 bits, and p2, p3, and p4 0 to p4 3 become part of the address bus. (2) selecting external data bus width the external data bus width can be set to 8 or 16 bits. (note, however, that only the separate bus can be set.) when the byte pin is l , the bus width is set to 16 bits; when h , it is set to 8 bits. (the internal bus width is permanently set to 16 bits.) while operating, fix the byte pin either to h or to l . (3) selecting separate/multiplex bus the bus format can be set to multiplex or separate bus using bits 4 and 5 of the processor mode register 0. ?separate bus in this mode, the data and address are input and output separately. the data bus can be set using the byte pin to be 8 or 16 bits. when the byte pin is h , the data bus is set to 8 bits and p0 functions as the data bus and p1 as a programmable i/o port. when the byte pin is l , the data bus is set to 16 bits and p0 and p1 are both used for the data bus. when the separate bus is used for access, a software wait can be selected. ?multiplex bus in this mode, data and address i/o are time multiplexed. with an 8-bit data bus selected (byte pin = h ), the 8 bits from d 0 to d 7 are multiplexed with a 0 to a 7 . with a 16-bit data bus selected (byte pin = l ), the 8 bits from d 0 to d 7 are multiplexed with a 1 to a 8 . d 8 to d 15 are not multiplexed. in this case, the external devices connected to the multiplexed bus are mapped to the microcomputer s even addresses (every 2nd address). to access these external de- vices, access the even addresses as bytes. the ale signal latches the address. it is output from p5 6 . before using the multiplex bus for access, be sure to insert a software wait. if the entire space is of multiplexed bus in memory expansion mode, choose an 8-bit width. the processor operates using the separate bus after reset os revoked, so the entire spacemultiplexed bus cannot be chosen on microprocessor mode. the higher-order address become a port of the entire space multiplexed bus is chosen, so only 256 bytes can be used in each chip select. 2.4.1 bus settings the byte pin and bits 4 to 6 of the processor mode register 0 (address 0004 16 ) are used to change the bus settings.table 2.4.1 shows the factors used to change the bus settings.
24 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP table 2.4.2 pin functions for processor mode p 5 6 i / o p o r t a l ea l ea l ea l ea l e p 5 7 i / o p o r t r d yr d yr d yr d yr d y p 0 0 t o p 0 7 i / o p o r td a t a b u sd a t a b u sd a t a b u sd a t a b u si / o p o r t ( s e p a r a t e b u s ) m e m o r y e x p a n s i o n m o d e / m i c r o p r o c e s s o r m o d e s d a t a b u s w i d t h b y t e p i n l e v e l p o r t p 4 0 t o p 4 3 f u n c t i o n s e l e c t b i t = 0 0 0 8 b i t s h 1 6 b i t s l 8 b i t s h 1 6 b i t s l n o t e 1 : i f t h e e n t i r e s p a c e i s o f m u l t i p l e x e d b u s i n m e m o r y e x p a n s i o n m o d e , c h o s e a n 8 - b i t w i d t h . t h e p r o c e s s o r o p e r a t e s u s i n g t h e s e p a r a t e b u s a f t e r r e s e t i s r e v o k e d , s o t h e e n t i r e s p a c e m u l t i p l e x e d b u s c a n n o t b e c h o s e n i n m i c r o p r o c e s s o r m o d e . t h e h i g h e r - o r d e r a d d r e s s b e c o m e s a p o r t i f t h e e n t i r e s p a c e m u l t i p l e x e d b u s i s c h o s e n , s o o n l y 2 5 6 b y t e s c a n b e u s e d i n e a c h c h i p s e l e c t . 2 : a d d r e s s b u s w h e n i n s e p a r a t e b u s m o d e . p r o c e s s o r m o d e m u l t i p l e x e d b u s s p a c e s e l e c t b i t c s ( c h i p s e l e c t ) o r p r o g r a m m a b l e i / o p o r t ( f o r d e t a i l s , r e f e r t o b u s c o n t r o l ) o u t p u t s r d , w r l , w r h , a n d b c l k o r r d , b h e , w r , a n d b c l k ( f o r d e t a i l s , r e f e r t o b u s c o n t r o l ) p o r t p 4 0 t o p 4 3 f u n c t i o n s e l e c t b i t = 1 p 1 0 t o p 1 7 i / o p o r ti / o p o r td a t a b u si / o p o r td a t a b u si / o p o r t p 2 1 t o p 2 7 i / o p o r t a d d r e s s b u sa d d r e s s b u s a d d r e s s b u sa d d r e s s b u sa d d r e s s b u s / d a t a b u s ( n o t e ) / d a t a b u s ( n o t e ) / d a t a b u s p 2 0 i / o p o r t a d d r e s s b u s a d d r e s s b u sa d d r e s s b u sa d d r e s s b u sa d d r e s s b u s / d a t a b u s ( n o t e ) / d a t a b u s p 3 0 i / o p o r ta d d r e s s b u s a d d r e s s b u s a d d r e s s b u sa d d r e s s b u sa 8 / d 7 / d a t a b u s ( n o t e ) p 3 1 t o p 3 7 i / o p o r ta d d r e s s b u sa d d r e s s b u sa d d r e s s b u sa d d r e s s b u si / o p o r t p 4 0 t o p 4 3 i / o p o r ti / o p o r ti / o p o r ti / o p o r ti / o p o r ti / o p o r t p 4 0 t o p 4 3 i / o p o r ta d d r e s s b u sa d d r e s s b u sa d d r e s s b u sa d d r e s s b u si / o p o r t p 4 4 t o p 4 7 i / o p o r t p 5 0 t o p 5 3 i / o p o r t p 5 4 i / o p o r t h l d ah l d ah l d ah l d ah l d a p 5 5 i / o p o r t h o l dh o l dh o l dh o l dh o l d e i t h e r c s 1 o r c s 2 i s f o r m u l t i p l e x e d b u s a n d o t h e r s a r e f o r s e p a r a t e b u s 0 1 s i n g l e - c h i p m o d e m e m o r y e x p a n s i o n m o d e 8 b i t s h mu l t i p l e x e d b u s f o r t h e e n t i r e s p a c e 1 1 ( n o t e 1 )
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 25 rev. 1.0 M306H2MC-XXXFP 2.4.2 bus control the following explains the signals required for accessing external devices and software waits. the signals required for accessing the external devices are valid when the processor mode is set to memory expansion mode and microprocessor mode. the software waits are valid in all processor modes. (1) address bus/data bus the address bus consists of the 20 pins a 0 to a 19 for accessing the 1m bytes of address space. the data bus consists of the pins for data i/o. when the byte pin is h , the 8 ports d 0 to d 7 function as the data bus. when byte is l , the 16 ports d 0 to d 15 function as the data bus. when a change is made from single-chip mode to memory expansion mode, the value of the address bus is undefined until external memory is accessed. (2) chip select signal the chip select signal is output using the same pins asp4 4 to p4 7 . bits 0 to 3 of the chip select control register (address 0008 16 ) set each pin to function as a port or to output the chip select signal. the chip select control register is valid in memory expansion mode and microprocessor mode. in single-chip mode,p4 4 to p4 7 function as programmable i/o ports regardless of the value in the chip select control register. _______ in microprocessor mode, only cs0 outputs the chip select signal after the reset state has been _______ _______ cancelled. cs1 to cs3 function as input ports. figure 2.4.3 shows the chip select control register. the chip select signal can be used to split the external area. tables 2.4.3 show the external memory areas specified using the chip select signal. figure 2.4.3 chip select control register p r o c e s s o r m o d e c h i p s e l e c t s i g n a l c s 0 m e m o r y e x p a n s i o n m o d e c s 1 2 8 0 0 0 1 6 t o 2 f f f f 1 6 ( 3 2 k b y t e s ) 3 0 0 0 0 1 6 t o c f f f f 1 6 ( 6 4 0 k b y t e s ) c s 3 0 4 0 0 0 1 6 t o 0 7 f f f 1 6 ( 1 6 k b y t e s ) m i c r o p r o c e s s o r m o d e 3 0 0 0 0 1 6 t o f f f f f 1 6 ( 8 3 2 k b y t e s ) c s 2 0 8 0 0 0 1 6 t o 2 7 f f f 1 6 ( 1 2 8 k b y t e s ) table 2.4.3 external areas specified by the chip select signals w f u n c t i o n b i t s y m b o l b i t n a m e c h i p s e l e c t c o n t r o l r e g i s t e r s y m b o la d d r e s s w h e n r e s e t c s r0 0 0 8 1 6 0 1 1 6 r b 7b 6b 5b 4b 3b 2b 1b 0 c s 0 0 : c h i p s e l e c t o u t p u t d i s a b l e d ( n o r m a l p o r t p i n ) 1 : c h i p s e l e c t o u t p u t e n a b l e d c s 0 o u t p u t e n a b l e b i t c s 1 c s 3 w c s 3 w a i t b i t c s 0 w c s 0 w a i t b i t c s 2 c s 2 o u t p u t e n a b l e b i t c s 1 o u t p u t e n a b l e b i t 0 : w a i t s t a t e i n s e r t e d 1 : n o w a i t s t a t e c s 2 w c s 2 w a i t b i t c s 2 w c s 1 w a i t b i t c s 3 c s 3 o u t p u t e n a b l e b i t
26 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP _____ ______ ________ table 2.4.5 operation of rd, wr, and bhe signals status of external data bus rd bhe wr hll lhl hlh lhh write 1 byte of data to odd address read 1 byte of data from odd address write 1 byte of data to even address read 1 byte of data from even address data bus width a0 h h l l hll l lhl l hl h / l lh h / l 8-bit (byte = h ) write data to both even and odd addresses read data from both even and odd addresses write 1 byte of data read 1 byte of data 16-bit (byte = l ) not used not used status of external data bus read data write 1 byte of data to even address write 1 byte of data to odd address write data to both even and odd addresses wrh wrl rd data bus width 16-bit (byte = l ) h h h h l h l h h l l l _____ ________ _________ table 2.4.4 operation of rd, wrl, and wrh signals (3) read/write signals with a 16-bit data bus (byte pin = l ), bit 2 of the processor mode register 0 (address 0004 16 ) select _____ ________ ______ _____ ________ _________ the combinations of rd, bhe, and wr signals or rd, wrl, and wrh signals. with an 8-bit data bus _____ ______ _______ (byte pin = h ), use the combination of rd, wr, and bhe signals. (set bit 2 of the processor mode register 0 (address 0004 16 ) to 0 .) tables 2.4.4 and 2.4.5 show the operation of these signals. _____ ______ ________ after a reset has been cancelled, the combination of rd, wr, and bhe signals is automatically selected. _____ _________ _________ when switching to the rd, wrl, and wrh combination, do not write to external memory until bit 2 of the processor mode register 0 (address 0004 16 ) has been set (note). note: before attempting to change the contents of the processor mode register 0, set bit 1 of the protect register (address 000a 16 ) to 1 . (4) ale signal the ale signal latches the address when accessing the multiplex bus space. latch the address when the ale signal falls. figure 2.4.4 ale signal and address/data bus when byte pin = h when byte pin = l ale address data (notes 1) address (notes 2) d 0 /a 0 to d 7 /a 7 a 8 to a 19 ale address data (notes 1) address d 0 /a 1 to d 7 /a 8 a 9 to a 19 address a 0 notes 1: floating when reading notes 2: when multiplexed bus for the entire space is selected,these are i/o ports.
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 27 rev. 1.0 M306H2MC-XXXFP _____ ________ figure 2.4.5 example of rd signal extended by rdy signal bclk rd cs i (i=0 to 3) rdy tsu(rdy - bclk) aaaa bclk rd cs i (i=0 to 3) rdy tsu(rdy - bclk) aaaaaa aaaaaa aa aa in an instance of separate bus in an instance of multiplexed bus accept timing of rdy signal : wait using rdy signal : wait using software accept timing of rdy signal ________ note: the rdy signal cannot be received immediately prior to a software wait. table 2.4.6 microcomputer status in ready state (note) item status oscillation on ___ _____ r/w signal, address bus, data bus, cs ________ maintain status when rdy signal received __________ ale signal, hlda, programmable i/o ports internal peripheral circuits on ________ (5) the rdy signal ________ rdy is a signal that facilitates access to an external device that requires long access time. as shown ________ in figure 2.4.5, if an l is being input to the rdy at the bclk falling edge, the bus turns to the wait ________ state. if an h is being input to the rdy pin at the bclk falling edge, the bus cancels the wait state. table 2.4.6 shows the state of the microcomputer with the bus in the wait state, and figure 2.4.5 ____ ________ shows an example in which the rd signal is prolonged by the rdy signal. ________ the rdy signal is valid when accessing the external area during the bus cycle in which bits 4 to 7 of ________ the chip select control register (address 0008 16 ) are set to 0 . the rdy signal is invalid when setting ________ 1 to all bits 4 to 7 of the chip select control register (address 0008 16 ), but the rdy pin should be treated as properly as in non-using.
28 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP table 2.4.7 microcomputer status in hold state item status oscillation on ___ _____ _______ r/w signal, address bus, data bus, cs, bhe floating programmable i/o ports p0, p1, p2, p3, p4, p5 floating p6, p7, p8, p9, p10 maintains status when hold signal is received __________ hlda output l internal peripheral circuits on (but watchdog timer stops) ale signal undefined __________ hold > dmac > cpu (6) hold signal the hold signal is used to transfer the bus privileges from the cpu to the external circuits. inputting l __________ to the hold pin places the microcomputer in the hold state at the end of the current bus access. this __________ __________ status is maintained and l is output from the hlda pin as long as l is input to the hold pin. table 2.4.7 shows the microcomputer status in the hold state. __________ bus-using priorities are given to hold, dmac, and cpu in order of decreasing precedence. figure 2.4.6 bus-using priorities (7) external bus status when the internal area is accessed table 2.4.8 shows the external bus status when the internal area is accessed. table 2.4.8 external bus status when the internal area is accessed item sfr accessed internal ram accessed address bus address output maintain status before accessed address of external area data bus when read floating floating when write output data undefined rd, wr, wrl, wrh rd, wr, wrl, wrh output output "h" bhe bhe output maintain status before accessed status of external area cs output "h" output "h" ale output "l" output "l"
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 29 rev. 1.0 M306H2MC-XXXFP area bus status wait bit bits 4 to 7 of chip select control register bus cycle invalid 1 2 bclk cycles external memory area separate bus 0 1 1 bclk cycle separate bus 0 0 2 bclk cycles separate bus 1 0 (note) 2 bclk cycles multiplex bus 0 3 bclk cycles multiplex bus 1 3 bclk cycles 0 (note) sfr internal rom/ram 0 invalid 1 bclk cycle invalid invalid 2 bclk cycles note: when using the rdy signal, always set to 0 . 0 table 2.4.9 software waits and bus cycles (8) bclk output the user can choose the bclk output by use of bit 7 of processor mode register 0 (0004 16 ) (note). when set to 1 , the output floating. note: before attempting to change the contents of the processor mode register 0, set bit 1 of the protectregister (address 000a 16 ) to 1 . (9) software wait a software wait can be inserted by setting the wait bit (bit 7) of the processor mode register 1 (address 0005 16 ) (note) and bits 4 to 7 of the chip select control register (address 0008 16 ). a software wait is inserted in the internal rom/ram area and in the external memory area by setting the wait bit of the processor mode register 1. when set to 0 , each bus cycle is executed in one bclk cycle. when set to 1 , each bus cycle is executed in two or three bclk cycles. after the microcom- puter has been reset, this bit defaults to 0 . when set to 1 , a wait is applied to all memory areas (two or three bclk cycles), regardless of the contents of bits 4 to 7 of the chip select control register. set this bit after referring to the recommended operating conditions (main clock input oscillation fre- ________ quency) of the electric characteristics. however, when the user is using the rdy signal, the relevant bit in the chip select control register s bits 4 to 7 must be set to 0 . when the wait bit of the processor mode register 1 is 0 , software waits can be set independently for each areas selected using the chip select signal. bits 4 to 7 of the chip select control register corre- _______ _______ spond to chip selects cs0 to cs3. when one of these bits is set to 1 , the bus cycle is executed in one bclk cycle. when set to 0 , the bus cycle is executed in two or three bclk cycles. these bits default to 0 after the microcomputer has been reset. the sfr area is always accessed in two bclk cycles regardless of the setting of these control bits. also, insert a software wait if using the multiplex bus to access the external memory area. table 2.4.9 shows the software wait and bus cycles. figure 2.4.7 shows example bus timing when using software waits. note: before attempting to change the contents of the processor mode register 1, set bit 1 of the protect register (address 000a 16 ) to 1 .
30 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP figure 2.4.7 typical bus timings using software wait output input address address bus cycle (note 1) < separate bus (with wait) > bclk read signal write signal data bus address bus (note 2) chip select (note 2) bclk read signal address bus/ data bus chip select (note 2) address address address bus (note 2) data output address address input ale bus cycle (note 1) < multiplexed bus > write signal bclk read signal write signal address bus (note 2) address address bus cycle (note 1) < separate bus (no wait) > output data bus chip select (note 2) input note 1: these example timing charts indicate bus cycle length. after this bus cycle sometimes come read and write cycles in succession. note 2: the address bus and chip select may be extended depending on the cpu status such as that of the instruction queue buffer.
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 31 rev. 1.0 M306H2MC-XXXFP main clock generating circuit sub clock generating circuit use of clock ?cpu? operating clock source ?cpu? operating clock source ?internal peripheral units ?timer a/b? count clock operating clock source source usable oscillator ceramic or crystal oscillator crystal oscillator pins to connect oscillator x in , x out x cin , x cout oscillation stop/restart function available available oscillator status immediately after reset oscillating stopped other externally derived clock can be input microcomputer (built-in feedback resistor) x in x out externally derived clock open vcc vss microcomputer (built-in feedback resistor) x in x out r d c in c out (note) note: insert a damping resistor if required. the resistance will vary depending on the oscillator and the oscillation drive capacity setting. use the value recommended by the maker of the oscillator. when the oscillation drive capacity is set to low, check that oscillation is stable.also, if the oscillator manufacturer's data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between x in and x out following the instruction. microcomputer (built-in feedback resistor) x cin x cout externally derived clock open vcc vss note: insert a damping resistor if required. the resistance will vary depending on the oscillator and the oscillation drive capacity setting. use the value recommended by the maker of the oscillator. when the oscillation drive capacity is set to low, check that oscillation is stable.also, if the oscillator manufacturer's data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between x cin and x cout following the instruction. microcomputer (built-in feedback resistor) x cin x cout (note) c cin c cout r cd table 2.5.1 main clock and sub clock generating circuits figure 2.5.2 examples of sub clock figure 2.5.1 examples of main clock 2.5.1 example of oscillator circuit figure 2.5.1 shows some examples of the main clock circuit, one using an oscillator connected to the circuit, and the other one using an externally derived clock for input. figure 2.5.2 shows some ex- amples of sub clock circuits, one using an oscillator connected to the circuit, and the other one using an externally derived clock for input. circuit constants in figures 2.5.1 and 2.5.2 vary with each oscillator used. use the values recommended by the manufacturer of your oscillator. 2.5 clock generating circuit the clock generating circuit contains two oscillator circuits that supply the operating clock sources to the cpu and internal peripheral units.
32 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP sub clock cm04 f c32 cm0i : bit i at address 0006 16 cm1i : bit i at address 0007 16 wdci : bit i at address 000f 16 x cin cm10 1 write signal 1/32 x cout q s r wait instruction x out main clock cm05 f c cm02 f 1 q s r nmi interrupt request level judgment output reset software reset f c cm07=0 cm07=1 f ad aaaa aaaa divider a d 1/2 1/2 1/2 1/2 cm06=0 cm17,cm16=00 cm06=0 cm17,cm16=01 cm06=0 cm17,cm16=10 cm06=1 cm06=0 cm17,cm16=11 d a details of divider x in f 8 f 32 c b b 1/2 c f 32 sio2 f 8 sio2 f 1 sio2 bclk figure 2.5.3 clock generating circuit 2.5.2 clock control figure 2.5.3 shows the block diagram of the clock generating circuit.
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 33 rev. 1.0 M306H2MC-XXXFP the following paragraphs describes the clocks generated by the clock generating circuit. (1) main clock the main clock is generated by the main clock oscillation circuit. after a reset, the clock is divided by 8 to the bclk. the clock can be stopped using the main clock stop bit (bit 5 at address 0006 16 ). stopping the clock, after switching the operating clock source of cpu to the sub-clock, reduces the power dissipation.after the oscillation of the main clock oscillation circuit has stabilized, the drive capacity of the main clock oscillation circuit can be reduced using the x in -x out drive capacity select bit (bit 5 at address 0007 16 ). reducing the drive capacity of the main clock oscillation circuit reduces the power dissipation. this bit changes to 1 when shifting from high-speed/medium-speed mode to stop mode and at a reset. when shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. (2) sub-clock the sub-clock is generated by the sub-clock oscillation circuit. no sub-clock is generated after a reset. after oscillation is started using the port xc select bit (bit 4 at address 0006 16 ), the sub-clock can be selected as the bclk by using the system clock select bit (bit 7 at address 0006 16 ). however, be sure that the sub-clock oscillation has fully stabilized before switching. after the oscillation of the sub-clock oscillation circuit has stabilized, the drive capacity of the sub-clock oscillation circuit can be reduced using the x cin -x cout drive capacity select bit (bit 3 at address 0006 16 ). reducing the drive capacity of the sub-clock oscillation circuit reduces the power dissipation. this bit changes to 1 when shifting to stop mode and at a reset. (3) bclk the bclk is the clock that drives the cpu, and is fc or the clock is derived by dividing the main clock by 1, 2, 4, 8, or 16. the bclk is derived by dividing the main clock by 8 after a reset. the bclk signal can be output from bclk pin by the bclk output disable bit (bit 7 at address 0004 16 ) in the memory expansion and the microprocessor modes. the main clock division select bit 0(bit 6 at address 0006 16 ) changes to 1 when shifting from high- speed/medium-speed to stop mode and at reset. when shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. (4) peripheral function clock(f 1 , f 8 , f 32 , f 1sio2 , f 8sio2 ,f 32sio2 ,f ad ) the clock for the peripheral devices is derived from the main clock or by dividing it by 1, 8, or 32. the peripheral function clock is stopped by stopping the main clock or by setting the wait peripheral function clock stop bit (bit 2 at 0006 16 ) to 1 and then executing a wait instruction. (5) f c32 this clock is derived by dividing the sub-clock by 32. it is used for the timer a and timer b counts. (6) f c this clock has the same frequency as the sub-clock. it is used for the bclk and for the watchdog timer.
34 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP system clock control register 0 (note 1) symbol address when reset cm0 0006 16 48 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 0 0 : i/o port p5 7 0 1 : output f c 1 0 : output f 8 1 1 : output f 32 b1 b0 cm07 cm05 cm04 cm03 cm01 cm02 cm00 cm06 clock output function select bit (valid in single-chip mode only) wait peripheral function clock stop bit 0 : do not stop peripheral function clock in wait mode 1 : stop peripheral function clock in wait mode (note 8) x cin -x cout drive capacity select bit (note 2) 0 : low 1 : high port x c select bit 0 : i/o port 1 : x cin -x cout generation main clock (x in -x out ) stop bit (notes 3,4,5) 0 : on 1 : off main clock division select bit 0 (note 7) 0 : cm16 and cm17 valid 1 : division by 8 mode system clock select bit (note 6) 0 : x in , x out 1 : x cin , x cout note 1: set bit 0 of the protect register (address 000a 16 ) to 1 before writing to this register. note 2: changes to 1 when shifting to stop mode and at a reset. note 3: when entering power saving mode, main clock stops using this bit. when returning from stop mode and operating with x in , set this bit to 0 . when main clock oscillation is operating by itself, set system clock select bit (cm07) to 1 before setting this bit to 1 . note 4: when inputting external clock, only clock oscillation buffer is stopped and clock input is acceptable. note 5: if this bit is set to 1 , x out turns h . the built-in feedback resistor remains being connected, so x in turns pulled up to x out ( h ) via the feedback resistor. note 6: set port xc select bit (cm04) to 1 and stabilize the sub-clock oscillating before setting to this bit from 0 to 1 . do not write to both bits at the same time. and also, set the main clock stop bit (cm05) to 0 and stabilize the main clock oscillating before setting this bit from 1 to 0 . note 7: this bit changes to 1 when shifting from high-speed/medium-speed mode to stop mode and at a reset. when shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. note 8: f c32 is not included. do not set this bit to 1 in the low-speed/ low-power dissipation mode. note 9: when the x cin /x cout is used, set ports p8 6 and p8 7 as the input ports without pull-up. system clock control register 1 (note 1) symbol address when reset cm1 0007 16 20 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 cm10 all clock stop control bit (note4) 0 : clock on 1 : all clocks off (stop mode) note 1: set bit 0 of the protect register (address 000a 16 ) to 1 before writing to this register. note 2: this bit changes to 1 when shifting from high-speed/medium-speed mode to stop mode and at a reset. when shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. note 3: can be selected when bit 6 of the system clock control register 0 (address 0006 16 ) is 0 . if 1 , division mode is fixed at 8. note 4: if this bit is set to 1 , x out turns h , and the built-in feedback resistor is cut off. x cin and x cout turn high- impedance state. w r w r 0 0 reserved bit always set to 0 0 0 cm15 x in -x out drive capacity select bit (note 2) 0 : low 1 : high cm16 cm17 main clock division select bit 1 (note 3) 0 0 : no division mode 0 1 : division by 2 mode 1 0 : division by 4 mode 1 1 : division by 16 mode b7 b6 figure 2.5.4 clock control registers 0 and 1 figure 2.5.4 shows the system clock control registers 0 and 1.
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 35 rev. 1.0 M306H2MC-XXXFP 2.5.3 clock output in single-chip mode, the clock output function select bits (bits 0 and 1 at address 0006 16 ) enable f 8 , f 32 , or fc to be output from the p5 7 /clk out pin. when the wait peripheral function clock stop bit (bit 2 at address 0006 16 ) is set to 1 , the output of f 8 and f3 2 stops when a wait instruction is executed. 2.5.4 stop mode writing 1 to the main clock and sub-clock stop control bit (bit 0 at address 0007 16 ) stops oscillation and the microcomputer enters stop mode. in stop mode, the content of the internal ram is retained provided that v cc remains above 2v. the internal oscillator circuit of expansion function (data acquisition / humming function) stops oscilla- tion when expansion register xtal_vco, pdc_vco_on, vps_vco_on = "l". because the oscillation , bclk, f 1 to f 32 , f 1sio2 to f 32sio2 , f c , f c32 , and f ad stops in stop mode, periph- eral functions such as the a-d converter and watchdog timer do not function. however, timer a and timer b operate provided that the event counter mode is set to an external pulse, and uarti(i = 0 to 2) si/o3,4 functions provided an external clock is selected. table 2.5.2 shows the status of the ports in stop mode.stop mode is cancelled by a hardware reset or interrupt. if an interrupt is to be used to cancel stop mode, that interrupt must first have been enabled. if returning by an interrupt, that interrupt routine is executed.when shifting from high-speed/medium-speed mode to stop mode and at a reset, the main clock division select bit 0 (bit 6 at address 0006 16 ) is set to 1 . when shifting from low-speed/ low power dissipation mode to stop mode, the value before stop mode is retained. address bus,data bus,cs0 to cs3, retains status before wait mode bhe rd,wr,wrl,wrh h hlda,bclk h ale h port retains status before wait mode retains status before wait mode clk out when fc selected valid only in single-chip mode does not stop when f8,f32 selected valid only in single-chip mode does not stop when the wait peripheral function clock stop bit is 0 . when the wait peripheral function clock stop bit is 1 , the status immediately prior to entering wait mode is main- tained . table 2.5.2 port status during stop mode pin memory expansion mode single-chip mode microprocessor mode
36 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP 2.5.5 wait mode when a wait instruction is executed, the bclk stops and the microcomputer enters the wait mode. in this mode, oscillation continues but the bclkand watchdog timer stop. writing 1 to the wait peripheral function clock stop bit and executing a wait instruction stops the clock being supplied to the internal peripheral functions, allowing power dissipation to be reduced. however,peripheral func- tion clock fc32 does not stop so that the peripherals using fc32 do not contribute to the power saving. when the mcu running in low-speed or low power dissipation mode,do not enter wait mode with this bit set to 1 . table 2.5.3 shows the status of the ports in wait mode. wait mode is cancelled by a hardware reset or an interrupt. when using an interrupt to exit wait mode, make sure the interrupt used for that purpose is enabled and those not used for that purpose have their priority levels set to 0 before entering wait mode. when restored from wait mode by an interrupt, the microcomputer restarts operation from the interrupt routine using as bclk the clock with which it was operating when the wait instruction was executed. when using a hardware reset or nmi inter- rupt only, be sure to set the priority levels of all other interrupts to 0 before entering wait mode. _______ _______ address bus, data bus, cs0 to cs3 retains status before stop mode _______ bhe _____ ______ ________ _________ rd, wr, wrl, wrh h ________ hlda, bclk h ale h port retains status before wait mode retains status before wait mode clk out when fc selected valid only in single-chip mode does not stop when f 8 , f 32 selected valid only in single-chip mode does not stop when the wait peripheral function clock stop bit is 0 . when the wait peripheral function clock stop bit is 1 . the status immediately prior to entering wait mode is maintained. table 2.5.3 port status during wait mode pin memory expansion mode single-chip mode microprocessor mode
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 37 rev. 1.0 M306H2MC-XXXFP 01000invalid division by 2 mode 10000invalid division by 4 mode invalid invalid 0 1 0 invalid division by 8 mode 11000invalid division by 16 mode 00000invalid no-division mode invalid invalid 1 invalid 0 1 low-speed mode invalid invalid 1 invalid 1 1 low power dissipation mode 2.5.6 status transition of bclk power dissipation can be reduced and low-voltage operation achieved by changing the count source for bclk. table 2.5.4 shows the operating modes corresponding to the settings of system clock control registers 0 and 1. when reset, the device starts in division by 8 mode. the main clock division select bit 0 (bit 6 at address 0006 16 ) changes to 1 when shifting from high-speed/medium-speed to stop mode and at a reset. when shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. the following shows the operational modes of bclk. (1) division by 2 mode the main clock is divided by 2 to obtain the bclk. (2) division by 4 mode the main clock is divided by 4 to obtain the bclk. (3) division by 8 mode the main clock is divided by 8 to obtain the bclk. when reset, the device starts operating from this mode. before the user can go from this mode to no division mode, division by 2 mode, or division by 4 mode, the main clock must be oscillating stably. when going to low-speed or lower power dissipation mode, make sure the sub-clock is oscillating stably. (4) division by 16 mode the main clock is divided by 16 to obtain the bclk. (5) no-division mode the main clock is divided by 1 to obtain the bclk. (6) low-speed mode f c is used as the bclk. note that oscillation of both the main and sub clocks must have stabilized before transferring from this mode to another or vice versa. at least 2 to 3 seconds are required after the sub clock starts. therefore, the program must be written to wait until this clock has stabilized immediately after powering up and after stop mode is cancelled. (7) low power dissipation mode f c is the bclk and the main clock is stopped. note : before the count source for bclk can be changed from x in to x cin or vice versa, the clock to which the count source is going to be switched must be oscillating stably. allow a wait time in software for the oscillation to stabilize before switching over the clock. cm17 cm16 cm07 cm06 cm05 cm04 operating mode of bclk table 2.5.4 operating modes dictated by settings of system clock control registers 0 and 1 cm1i: bit i of address 0007 16 cm0i: bit i of address 0006 16
38 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP 2.5.7 power control the following is a description of the three available power control modes: modes power control is available in three modes. (a) normal operation mode ?high-speed mode divide-by-1 frequency of the main clock becomes the bclk. the cpu operates with the internal clock selected. each peripheral function operates according to its assigned clock. ?medium-speed mode divide-by-2, divide-by-4, divide-by-8, or divide-by-16 frequency of the main clock becomes the bclk. the cpu operates according to the internal clock selected. each peripheral function operates according to its assigned clock. ?low-speed mode f c becomes the bclk. the cpu operates according to the fc clock. the fc clock is supplied by the secondary clock. each peripheral function operates according to its assigned clock. ?low power dissipation mode the main clock operating in low-speed mode is stopped. the cpu operates according to the f c clock. the fc clock is supplied by the secondary clock. the only peripheral functions that operate are those with the sub-clock selected as the count source. when in single-chip mode, the device can be operated with a low supply voltage (v cc = 3.0 v) only during low power dissipation mode. before entering or exiting low power dissipation mode, always make sure the supply voltage v cc is 5 v. note : when operating with a low supply voltage, be aware that only the cpu, rom, ram, input/ output ports, timers (timers a and b), and the interrupt control circuit can be used. all other internal resources (e.g., data slicer, dmac, a/d, and d/a) cannot be used. (b) wait mode the cpu operation is stopped. the oscillators do not stop. (c) stop mode the main clock and the sub-clock oscillators stop. the cpu and all built-in peripheral functions stop. this mode, among the three modes listed here, is the most effective in decreasing power consumption. figure 2.5.5 is the state transition diagram of the above modes.
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 39 rev. 1.0 M306H2MC-XXXFP figure 2.5.5 state transition diagram of power control mode t r a n s i t i o n o f s t o p m o d e , w a i t m o d e t r a n s i t i o n o f n o r m a l m o d e m e d i u m - s p e e d m o d e ( d i v i d e d - b y - 8 m o d e ) b c l k : f ( x i n ) / 8 c m 0 7 = 0 c m 0 6 = 1 l o w - s p e e d m o d e h i g h - s p e e d m o d e m a i n c l o c k i s o s c i l l a t i n g s u b c l o c k i s s t o p p e d m a i n c l o c k i s o s c i l l a t i n g s u b c l o c k i s s t o p p e d m a i n c l o c k i s s t o p p e d s u b c l o c k i s o s c i l l a t i n g m a i n c l o c k i s o s c i l l a t i n g s u b c l o c k i s o s c i l l a t i n g l o w p o w e r d i s s i p a t i o n m o d e ( n o t e 5 ) r e s e t m a i n c l o c k i s s t o p p e d s u b c l o c k i s s t o p p e d m e d i u m - s p e e d m o d e ( d i v i d e d - b y - 8 m o d e ) i n t e r r u p t c m 1 0 = 1 s t o p m o d e w a i t m o d e c p u o p e r a t i o n s t o p p e d i n t e r r u p t w a i t i n s t r u c t i o n m a i n c l o c k i s s t o p p e d s u b c l o c k i s s t o p p e d h i g h - s p e e d / m e d i u m - s p e e d m o d e s t o p m o d e w a i t m o d e c p u o p e r a t i o n s t o p p e d i n t e r r u p t w a i t i n s t r u c t i o n c m 1 0 = 1 i n t e r r u p t m a i n c l o c k i s s t o p p e d s u b c l o c k i s s t o p p e d c p u o p e r a t i o n s t o p p e d l o w - s p e e d / l o w p o w e r d i s s i p a t i o n m o d e s t o p m o d e w a i t m o d e i n t e r r u p t w a i t i n s t r u c t i o n i n t e r r u p t c m 1 0 = 1 b c l k : f ( x i n ) / 2 c m 0 7 = 0 c m 0 6 = 0 c m 1 7 = 0 c m 1 6 = 1 m e d i u m - s p e e d m o d e ( d i v i d e d - b y - 2 m o d e ) b c l k : f ( x i n ) / 1 6 c m 0 7 = 0 c m 0 6 = 0 c m 1 7 = 1 c m 1 6 = 1 m e d i u m - s p e e d m o d e ( d i v i d e d - b y - 1 6 m o d e ) b c l k : f ( x i n ) / 4 c m 0 7 = 0 c m 0 6 = 0 c m 1 7 = 1 c m 1 6 = 0 m e d i u m - s p e e d m o d e ( d i v i d e d - b y - 4 m o d e ) b c l k : f ( x i n ) c m 0 7 = 0 c m 0 6 = 0 c m 1 7 = 0 c m 1 6 = 0 b c l k : f ( x i n ) / 8 m e d i u m - s p e e d m o d e ( d i v i d e d - b y - 8 m o d e ) c m 0 7 = 0 c m 0 6 = 1 h i g h - s p e e d m o d e b c l k : f ( x i n ) / 2 c m 0 7 = 0 c m 0 6 = 0 c m 1 7 = 0 c m 1 6 = 1 m e d i u m - s p e e d m o d e ( d i v i d e d - b y - 2 m o d e ) b c l k : f ( x i n ) / 1 6 c m 0 7 = 0 c m 0 6 = 0 c m 1 7 = 1 c m 1 6 = 1 m e d i u m - s p e e d m o d e ( d i v i d e d - b y - 1 6 m o d e ) b c l k : f ( x i n ) / 4 c m 0 7 = 0 c m 0 6 = 0 c m 1 7 = 1 c m 1 6 = 0 m e d i u m - s p e e d m o d e ( d i v i d e d - b y - 4 m o d e ) b c l k : f ( x i n ) c m 0 7 = 0 c m 0 6 = 0 c m 1 7 = 0 c m 1 6 = 0 b c l k : f ( x c i n ) c m 0 7 = 1 b c l k : f ( x c i n ) c m 0 7 = 1 m a i n c l o c k i s o s c i l l a t i n g s u b c l o c k i s o s c i l l a t i n g c m 0 7 = 0 ( n o t e 1 , 3 ) c m 0 7 = 0 ( n o t e 1 ) c m 0 6 = 1 c m 0 4 = 0 c m 0 7 = 1 ( n o t e 2 ) c m 0 7 = 0 ( n o t e 1 ) c m 0 6 = 0 ( n o t e 3 ) c m 0 4 = 1 c m 0 7 = 1 ( n o t e 2 ) c m 0 5 = 1 c m 0 5 = 0 c m 0 5 = 1 c m 0 4 = 0 c m 0 4 = 1 c m 0 6 = 0 ( n o t e s 1 , 3 ) c m 0 6 = 1 c m 0 4 = 0 c m 0 4 = 1 ( n o t e s 1 , 3 ) n o t e 1 : s w i t c h c l o c k a f t e r o s c i l l a t i o n o f m a i n c l o c k i s s u f f i c i e n t l y s t a b l e . n o t e 2 : s w i t c h c l o c k a f t e r o s c i l l a t i o n o f s u b c l o c k i s s u f f i c i e n t l y s t a b l e . n o t e 3 : c h a n g e c m 0 6 a f t e r c h a n g i n g c m 1 7 a n d c m 1 6 . n o t e 4 : t r a n s i t i n a c c o r d a n c e w i t h a r r o w . n o t e 5 : t h e d e v i c e c a n b e o p e r a t e d w i t h a l o w s u p p l y v o l t a g e ( v c c = 3 . 0 v ) i n o n l y l o w p o w e r dissipation m o d e . a l w a y s m a k e s u r e t h e p o w e r s u p p l y v o l t a g e v c c i s s w i t c h e d b e t w e e n 5 . 0 v a n d 3 . 0 v i n t h i s m o d e n o r m a l m o d e ( r e f e r t o t h e f o l l o w i n g f o r t h e t r a n s i t i o n o f n o r m a l m o d e . )
40 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP 2.6 protection the protection function is provided so that the values in important registers cannot be changed in the event that the program runs out of control. figure 2.6.1 shows the protect register. the values in the processor mode register 0 (address 0004 16 ), processor mode register 1 (address 0005 16 ), system clock control register 0 (address 0006 16 ), system clock control register 1 (address 0007 16 ), port p9 direction register (address 03f3 16 ) , si/o3 control register (address 0362 16 ) and si/o4 control register (address 0366 16 ) can only be changed when the respective bit in the protect register is set to 1 . therefore, important outputs can be allocated to port p9. if, after 1 (write-enabled) has been written to the port p9 direction register and si/oi control register (i=3,4) write-enable bit (bit 2 at address 000a 16 ), a value is written to any address, the bit automatically reverts to 0 (write-inhibited). however, the system clock control registers 0 and 1 write-enable bit (bit 0 at 000a 16 ) and processor mode register 0 and 1 write-enable bit (bit 1 at 000a 16 ) do not automatically return to 0 after a value has been written to an address. the program must therefore be written to return these bits to 0 . protect register symbol address when reset prcr 000a 16 xxxxx000 2 bit name bit symbol b7 b6 b5 b4 b3 b2 b1 b0 0 : write-inhibited 1 : write-enabled prc1 prc0 prc2 enables writing to processor mode registers 0 and 1 (addresses 0004 16 and 0005 16 ) function 0 : write-inhibited 1 : write-enabled enables writing to system clock control registers 0 and 1 (addresses 0006 16 and 0007 16 ) enables writing to port p9 direction register (address 03f3 16 ) and to si/oi control register (i=3,4) (addresses 0362 16 and 0366 16 ) (note) 0 : write-inhibited 1 : write-enabled w r aa aa a a aa a aa a nothing is assigned. in an attempt to write to these bits, write 0 . the value, if read, turns out to be indeterminate. note: writing a value to an address after 1 is written to this bit returns the bit to 0 . other bits do not automatically return to 0 and they must therefore be reset by the program. figure 2.6.1 protect register
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 41 rev. 1.0 M306H2MC-XXXFP ?maskable interrupt : an interrupt which can be enabled (disabled) by the interrupt enable flag (i flag) or whose interrupt priority can be changed by priority level. ?non-maskable interrupt : an interrupt which cannot be enabled (disabled) by the interrupt enable flag (i flag) or whose interrupt priority cannot be changed by priority level. figure 2.7.1 classification of interrupts interrupt ? ? ? ? ? ? ? ? ? software hardware ? ? ? ? ? special peripheral i/o (note) ? ? ? ? ? undefined instruction (und instruction) overflow (into instruction) brk instruction int instruction ? ? ? ? ? ? ? reset _______ nmi ________ dbc watchdog timer single step address matched note: peripheral i/o interrupts are generated by the peripheral functions built into the microcomputer system. 2.7 interrupt 2.7.1 interrupt figure 2.7.1 lists the types of interrupts.
42 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP 2.7.2 software interrupts a software interrupt occurs when executing certain instructions. software interrupts are non- maskable interrupts. ?undefined instruction interrupt an undefined instruction interrupt occurs when executing the und instruction. ?overflow interrupt an overflow interrupt occurs when executing the into instruction with the overflow flag (o flag) set to ?? the following are instructions whose o flag changes by arithmetic: abs, adc, adcf, add, cmp, div, divu, divx, neg, rmpa, sbb, sha, sub ?brk interrupt a brk interrupt occurs when executing the brk instruction. ?int interrupt an int interrupt occurs when assiging one of software interrupt numbers 0 through 63 and executing the int instruction. software interrupt numbers 0 through 31 are assigned to peripheral i/o inter- rupts, so executing the int instruction allows executing the same interrupt routine that a peripheral i/o interrupt does. the stack pointer (sp) used for the int interrupt is dependent on which software interrupt number is involved. so far as software interrupt numbers 0 through 31 are concerned, the microcomputer saves the stack pointer assignment flag (u flag) when it accepts an interrupt request. if change the u flag to ? and select the interrupt stack pointer (isp), and then execute an interrupt sequence. when returning from the interrupt routine, the u flag is returned to the state it was before the acceptance of interrupt request. so far as software numbers 32 through 63 are concerned, the stack pointer does not make a shift.
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 43 rev. 1.0 M306H2MC-XXXFP 2.7.3 hardware interrupts hardware interrupts are classified into two types ?special interrupts and peripheral i/o interrupts. (1) special interrupts special interrupts are non-maskable interrupts. ?reset ____________ reset occurs if an ??is input to the reset pin. _______ ?nmi interrupt _______ _______ an nmi interrupt occurs if an ??is input to the nmi pin. ________ ?dbc interrupt this interrupt is exclusively for the debugger, do not use it in other circumstances. ?watchdog timer interrupt generated by the watchdog timer. ?single-step interrupt this interrupt is exclusively for the debugger, do not use it in other circumstances. with the debug flag (d flag) set to ?? a single-step interrupt occurs after one instruction is executed. ?address match interrupt an address match interrupt occurs immediately before the instruction held in the address indicated by the address match interrupt register is executed with the address match interrupt enable bit set to ?? if an address other than the first address of the instruction in the address match interrupt register is set, no address match interrupt occurs. for address match interrupt, see 2.7.10 address match interrupt. (2) peripheral i/o interrupts a peripheral i/o interrupt is generated by one of built-in peripheral functions. built-in peripheral func- tions are dependent on classes of products, so the interrupt factors too are dependent on classes of products. the interrupt vector table is the same as the one for software interrupt numbers 0 through 31 the int instruction uses. peripheral i/o interrupts are maskable interrupts. ?bus collision detection interrupt this is an interrupt that the serial i/o bus collision detection generates. ?dma0 interrupt, dma1 interrupt these are interrupts that dma generates. ?key-input interrupt ___ a key-input interrupt occurs if an ??is input to the ki pin. ?a-d conversion interrupt this is an interrupt that the a-d converter generates. ?uart0, uart1, uart2/nack, si/o3 and si/o4 transmission interrupt these are interrupts that the serial i/o transmission generates. ?uart0, uart1, uart2/ack, si/o3 and si/o4 reception interrupt these are interrupts that the serial i/o reception generates. ?timer a0 interrupt through timer a4 interrupt these are interrupts that timer a generates ?timer b0 interrupt through timer b5 interrupt these are interrupts that timer b generates. ________ ________ ?int0 interrupt through int5 interrupt ______ ______ an int interrupt occurs if either a rising edge or a falling edge or a both edge is input to the int pin.
44 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP interrupt source vector table addresses remarks address (l) to address (h) undefined instruction fffdc 16 to fffdf 16 interrupt on und instruction overflow fffe0 16 to fffe3 16 interrupt on into instruction brk instruction fffe4 16 to fffe7 16 if the vector contains ff 16 , program execution starts from the address shown by the vector in the variable vector table address match fffe8 16 to fffeb 16 there is an address-matching interrupt enable bit single step (note) fffec 16 to fffef 16 do not use watchdog timer ffff0 16 to ffff3 16 ________ dbc (note) ffff4 16 to ffff7 16 do not use _______ nmi ffff8 16 to ffffb 16 _______ external interrupt by input to nmi pin reset ffffc 16 to fffff 16 note: interrupts used for debugging purposes only. figure 2.7.2 format for specifying interrupt vector addresses aaaaaaaaa aaaaaaaaa mid address aaaaaaaaa aaaaaaaaa low address aaaaaaaaa aaaaaaaaa 0 0 0 0 high address aaaaaaaaa aaaaaaaaa 0 0 0 0 0 0 0 0 vector address + 0 vector address + 1 vector address + 2 vector address + 3 lsb msb 2.7.4 interrupts and interrupt vector tables if an interrupt request is accepted, a program branches to the interrupt routine set in the interrupt vector table. set the first address of the interrupt routine in each vector table. figure 2.7.2 shows the format for specifying the address. two types of interrupt vector tables are available fixed vector table in which addresses are fixed and variable vector table in which addresses can be varied by the setting. ?fixed vector tables the fixed vector table is a table in which addresses are fixed. the vector tables are located in an area extending from fffdc 16 to fffff 16 . one vector table comprises four bytes. set the first address of interrupt routine in each vector table. table 2.7.1 shows the interrupts assigned to the fixed vector tables and addresses of vector tables. table 2.7.1 interrupts assigned to the fixed vector tables and addresses of vector tables
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 45 rev. 1.0 M306H2MC-XXXFP software interrupt number interrupt source vector table address address (l) to address (h) remarks cannot be masked i flag +0 to +3 (note 1) brk instruction software interrupt number 0 +44 to +47 (note 1) software interrupt number 11 +48 to +51 (note 1) software interrupt number 12 +52 to +55 (note 1) software interrupt number 13 +56 to +59 (note 1) software interrupt number 14 +68 to +71 (note 1) software interrupt number 17 +72 to +75 (note 1) software interrupt number 18 +76 to +79 (note 1) software interrupt number 19 +80 to +83 (note 1) software interrupt number 20 +84 to +87 (note 1) software interrupt number 21 +88 to +91 (note 1) software interrupt number 22 +92 to +95 (note 1) software interrupt number 23 +96 to +99 (note 1) software interrupt number 24 +100 to +103 (note 1) software interrupt number 25 +104 to +107 (note 1) software interrupt number 26 +108 to +111 (note 1) software interrupt number 27 +112 to +115 (note 1) software interrupt number 28 +116 to +119 (note 1) software interrupt number 29 +120 to +123 (note 1) software interrupt number 30 +124 to +127 (note 1) software interrupt number 31 +128 to +131 (note 1) software interrupt number 32 +252 to +255 (note 1) software interrupt number 63 to note 1: address relative to address in interrupt table register (intb). note 2: it is selected by interrupt request cause bit (bit 6, 7 in address 035f 16 ). note 3: when iic mode is selected, nack and ack interrupts are selected. cannot be masked i flag +40 to +43 (note 1) software interrupt number 10 +60 to +63 (note 1) software interrupt number 15 +64 to +67 (note 1) software interrupt number 16 +20 to +23 (note 1) software interrupt number 5 +24 to +27 (note 1) software interrupt number 6 +28 to +31 (note 1) software interrupt number 7 +32 to +35 (note 1) software interrupt number 8 +16 to +19 (note 1) int3 software interrupt number 4 +36 to +39 (note 1) si/o3/int4 software interrupt number 9 si/o4/int5 timer b3 timer b4 timer b5 (note 2) (note 2) to dma0 dma1 key input interrupt a-d uart0 transmit uart0 receive uart1 transmit uart1 receive timer a0 timer a1 timer a2 timer a3 timer a4 timer b0 timer b1 timer b2 int0 int1 int2 software interrupt bus collision detection uart2 transmit/nack (note 3) uart2 receive/ack (note 3) table 2.7.2 interrupts assigned to the variable vector tables and addresses of vector tables ?variable vector tables the addresses in the variable vector table can be modified, according to the user s settings. indi- cate the first address using the interrupt table register (intb). the 256-byte area subsequent to the address the intb indicates becomes the area for the variable vector tables. one vector table com- prises four bytes. set the first address of the interrupt routine in each vector table. table 2.7.2 shows the interrupts assigned to the variable vector tables and addresses of vector tables.
46 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP 2.7.5 interrupt control descriptions are given here regarding how to enable or disable maskable interrupts and how to set the priority to be accepted. what is described here does not apply to non-maskable interrupts. enable or disable a maskable interrupt using the interrupt enable flag (i flag), interrupt priority level selection bit, or processor interrupt priority level (ipl). whether an interrupt request is present or absent is indicated by the interrupt request bit. the interrupt request bit and the interrupt priority level selection bit are located in the interrupt control register of each interrupt. also, the interrupt enable flag (i flag) and the ipl are located in the flag register (flg). figure 2.7.3 shows the memory map of the interrupt control registers.
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 47 rev. 1.0 M306H2MC-XXXFP symbol address when reset intiic(i=3) 0044 16 xx00x000 2 siic/intjic (i=4, 3) 0048 16 , 0049 16 xx00x000 2 (j=5, 4) intiic(i=0 to 2) 005d 16 to 005f 16 xx00x000 2 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 a a aa aa ilvl0 ir pol nothing is assigned. in an attempt to write to these bits, write 0. the value, if read, turns out to be 0. interrupt priority level select bit interrupt request bit polarity select bit reserved bit 0: interrupt not requested 1: interrupt requested 0 : selects falling edge 1 : selects rising edge always set to 0 ilvl1 ilvl2 note 1: this bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1). note 2: to rewrite the interrupt control register, do so at a point that dose not generate the interrupt request for that register. for details, see the precautions for interrupts. (note 1) interrupt control register b7 b6 b5 b4 b3 b2 b1 b0 a a aa aa aa aa a a bit name function bit symbol w r symbol address when reset tbiic(i=3 to 5) 0045 16 to 0047 16 xxxxx000 2 bcnic 004a 16 xxxxx000 2 dmiic(i=0, 1) 004b 16 , 004c 16 xxxxx000 2 kupic 004d 16 xxxxx000 2 adic 004e 16 xxxxx000 2 sitic(i=0 to 2) 0051 16 , 0053 16 , 004f 16 xxxxx000 2 siric(i=0 to 2) 0052 16 , 0054 16 , 0050 16 xxxxx000 2 taiic(i=0 to 4) 0055 16 to 0059 16 xxxxx000 2 tbiic(i=0 to 2) 005a 16 to 005c 16 xxxxx000 2 ilvl0 ir interrupt priority level select bit interrupt request bit 0 : interrupt not requested 1 : interrupt requested ilvl1 ilvl2 nothing is assigned. in an attempt to write to these bits, write 0. the value, if read, turns out to be 0. (note 1) note 1: this bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1). note 2: to rewrite the interrupt control register, do so at a point that dose not generate the interrupt request for that register. for details, see the precautions for interrupts. 0 0 0 : level 0 (interrupt disabled) 0 0 1 : level 1 0 1 0 : level 2 0 1 1 : level 3 1 0 0 : level 4 1 0 1 : level 5 1 1 0 : level 6 1 1 1 : level 7 b2 b1 b0 0 0 0 : level 0 (interrupt disabled) 0 0 1 : level 1 0 1 0 : level 2 0 1 1 : level 3 1 0 0 : level 4 1 0 1 : level 5 1 1 0 : level 6 1 1 1 : level 7 b2 b1 b0 0 a a a a a a a a a a a a a a a a a a a a a a figure 2.7.3 interrupt control registers
48 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP (1) interrupt enable flag (i flag) the interrupt enable flag (i flag) controls the enabling and disabling of maskable interrupts. setting this flag to 1 enables all maskable interrupts; setting it to 0 disables all maskable interrupts. this flag is set to 0 after reset. (2) interrupt request bit the interrupt request bit is set to "1" by hardware when an interrupt is requested. after the interrupt is accepted and jumps to the corresponding interrupt vector, the request bit is set to "0" by hardware. the interrupt request bit can also be set to "0" by software. (do not set this bit to "1"). (3) interrupt priority level select bit and processor interrupt priority level (ipl) set the interrupt priority level using the interrupt priority level select bit, which is one of the component bits of the interrupt control register. when an interrupt request occurs, the interrupt priority level is compared with the ipl. the interrupt is enabled only when the priority level of the interrupt is higher than the ipl. therefore, setting the interrupt priority level to 0 disables the interrupt. table 2.7.3 shows the settings of interrupt priority levels and table 2.7.4 shows the interrupt levels enabled, according to the consist of the ipl. the following are conditions under which an interrupt is accepted: interrupt enable flag (i flag) = 1 interrupt request bit = 1 interrupt priority level > ipl the interrupt enable flag (i flag), the interrupt request bit, the interrupt priority select bit, and the ipl are independent, and they are not affected by one another. table 2.7.4 interrupt levels enabled according to the contents of the ipl table 2.7.3 settings of interrupt priority levels interrupt priority level select bit interrupt priority level priority order 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 level 0 (interrupt disabled) level 1 level 2 level 3 level 4 level 5 level 6 level 7 low high b2 b1 b0 enabled interrupt priority levels 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 interrupt levels 1 and above are enabled interrupt levels 2 and above are enabled interrupt levels 3 and above are enabled interrupt levels 4 and above are enabled interrupt levels 5 and above are enabled interrupt levels 6 and above are enabled interrupt levels 7 and above are enabled all maskable interrupts are disabled ipl 2 ipl 1 ipl 0 ipl
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 49 rev. 1.0 M306H2MC-XXXFP example 1: int_switch1: fclr i ; disable interrupts. and.b #00h, 0055h ; clear ta0ic int. priority level and int. request bit. nop ; four nop instructions are required when using hold function. nop fset i ; enable interrupts. example 2: int_switch2: fclr i ; disable interrupts. and.b #00h, 0055h ; clear ta0ic int. priority level and int. request bit. mov.w mem, r0 ; dummy read. fset i ; enable interrupts. example 3: int_switch3: pushc flg ; push flag register onto stack fclr i ; disable interrupts. and.b #00h, 0055h ; clear ta0ic int. priority level and int. request bit. popc flg ; enable interrupts. the reason why two nop instructions (four when using the hold function) or dummy read are inserted before fset i in examples 1 and 2 is to prevent the interrupt enable flag i from being set before the interrupt control register is rewritten due to effects of the instruction queue. (4) rewrite the interrupt control register to rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register. if there is possibility of the interrupt request occur, rewrite the interrupt control register after the interrupt is disabled. the program examples are described as follow: when a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the interrupt request bit is not set sometimes even if the interrupt request for that register has been gener- ated. this will depend on the instruction. if this creates problems, use the below instructions to change the register. instructions : and, or, bclr, bset
50 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP 2.7.6 interrupt sequence an interrupt sequence what are performed over a period from the instant an interrupt is accepted to the instant the interrupt routine is executed is described here. if an interrupt occurs during execution of an instruction, the processor determines its priority when the execution of the instruction is completed, and transfers control to the interrupt sequence from the next cycle. if an interrupt occurs during execution of either the smovb, smovf, sstr or rmpa instruc- tion, the processor temporarily suspends the instruction being executed, and transfers control to the interrupt sequence. in the interrupt sequence, the processor carries out the following in sequence given: (a) cpu gets the interrupt information (the interrupt number and interrupt request level) by reading address 00000 16 . (b) saves the content of the flag register (flg) as it was immediately before the start of interrupt sequence in the temporary register (note) within the cpu. (c) sets the interrupt enable flag (i flag), the debug flag (dflag), and the stack pointer select flag (u flag) to 0 (the u flag, however does not change if the int instruction, in software interrupt numbers 32 through 63, is executed) (d) saves the content of the temporary register (note) within the cpu in the stack area. (e) saves the content of the program counter (pc) in the stack area. ( f) sets the interrupt priority level of the accepted instruction in the ipl. after the interrupt sequence is completed, the processor resumes executing instructions from the first address of the interrupt routine. note: this register cannot be utilized by the user. (1) interrupt response time 'interrupt response time' is the period between the instant an interrupt occurs and the instant the first instruction within the interrupt routine has been executed. this time comprises the period from the occurrence of an interrupt to the completion of the instruction under execution at that moment (a) and the time required for executing the interrupt sequence (b). figure 2.7.4 shows the interrupt response time. instruction interrupt sequence instruction in interrupt routine time interrupt response time (a) (b) interrupt request acknowledged interrupt request generated (a) time from interrupt request is generated to when the instruction then under execution is completed. (b) time in which the instruction sequence is executed. figure 2.7.4 interrupt response time
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 51 rev. 1.0 M306H2MC-XXXFP interrupt sources without priority levels 7 value set in the ipl _______ watchdog timer, nmi other not changed 0 stack pointer (sp) value interrupt vector address 16-bit bus, without wait 8-bit bus, without wait even even odd (note 2) odd (note 2) even odd even odd 18 cycles (note 1) 19 cycles (note 1) 19 cycles (note 1) 20 cycles (note 1) 20 cycles (note 1) 20 cycles (note 1) 20 cycles (note 1) 20 cycles (note 1) reset indeterminate 123456789 1011 12 13 14 15 16 17 18 the indeterminate segment is dependent on the queue buffer. if the queue buffer is ready to take an instruction, a read cycle occurs. indeterminate sp-2 contents sp-4 contents vec contents vec+2 contents interrupt information address 0000 indeterminate sp-2 sp-4 vec vec+2 pc bclk address bus data bus w r table 2.7.6 relationship between interrupts without interrupt priority levels and ipl (2) variation of ipl when interrupt request is accepted if an interrupt request is accepted, the interrupt priority level of the accepted interrupt is set in the ipl. if an interrupt request, that does not have an interrupt priority level, is accepted, one of the values shown in table 2.7.6 is set in the ipl. figure 2.7.5 time required for executing the interrupt sequence ________ notes 1: add 2 cycles in the case of a dbc interrupt; add 1 cycle in the case either of an address coincidence interrupt or of a single-step interrupt. notes 2: locate an interrupt vector address in an even address, if possible. table 2.7.5 time required for executing the interrupt sequence time (a) is dependent on the instruction under execution. thirty cycles is the maximum required for the divx instruction (without wait). time (b) is as shown in table 2.7.5
52 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP (3) saving registers in the interrupt sequence, only the contents of the flag register (flg) and that of the program counter (pc) are saved in the stack area. first, the processor saves the four higher-order bits of the program counter, and 4 upper-order bits and 8 lower-order bits of the flg register, 16 bits in total, in the stack area, then saves 16 lower-order bits of the program counter. figure 2.7.6 shows the state of the stack as it was before the acceptance of the interrupt request, and the state the stack after the acceptance of the interrupt request. save other necessary registers at the beginning of the interrupt routine using software. using the pushm instruction alone can save all the registers except the stack pointer (sp). address content of previous stack stack area [sp] stack pointer value before interrupt occurs m m 1 m 2 m 3 m 4 stack status before interrupt request is acknowledged stack status after interrupt request is acknowledged content of previous stack m + 1 msb lsb m m 1 m 2 m 3 m 4 address flag register (flg l ) content of previous stack stack area flag register (flg h ) program counter (pc h ) [sp] new stack pointer value content of previous stack m + 1 msb lsb program counter (pc l ) program counter (pc m ) figure 2.7.6 state of stack before and after acceptance of interrupt request
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 53 rev. 1.0 M306H2MC-XXXFP (2) stack pointer (sp) contains odd number [sp] (odd) [sp] 1 (even) [sp] 2(odd) [sp] 3 (even) [sp] 4(odd) [sp] 5 (even) address sequence in which order registers are saved (2) (1) finished saving registers in four operations. (3) (4) (1) stack pointer (sp) contains even number [sp] (even) [sp] 1(odd) [sp] 2 (even) [sp] 3 (odd) [sp] 4 (even) [sp] 5 (odd) note: [sp] denotes the initial value of the stack pointer (sp) when interrupt request is acknowledged. after registers are saved, the sp content is [sp] minus 4. address program counter (pc m ) stack area flag register (flg l ) program counter (pc l ) sequence in which order registers are saved (2) saved simultaneously, all 16 bits (1) saved simultaneously, all 16 bits finished saving registers in two operations. program counter (pc m ) stack area flag register (flg l ) program counter (pc l ) saved simultaneously, all 8 bits flag register (flg h ) program counter (pc h ) flag register (flg h ) program counter (pc h ) the operation of saving registers carried out in the interrupt sequence is dependent on whether the content of the stack pointer, at the time of acceptance of an interrupt request, is even or odd. if the content of the stack pointer (note) is even, the content of the flag register (flg) and the content of the program counter (pc) are saved, 16 bits at a time. if odd, their contents are saved in two steps, 8 bits at a time. figure 2.7.7 shows the operation of the saving registers. note: when any int instruction in software numbers 32 to 63 has been executed, this is the stack pointer indicated by the u flag. otherwise, it is the interrupt stack pointer (isp). figure 2.7.7 operation of saving registers
54 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP (5) interrupt priority if there are two or more interrupt requests occurring at a point in time within a single sampling (check- ing whether interrupt requests are made), the interrupt assigned a higher priority is accepted. assign an arbitrary priority to maskable interrupts (peripheral i/o interrupts) using the interrupt priority level select bit. if the same interrupt priority level is assigned, however, the interrupt assigned a higher hardware priority is accepted. priorities of the special interrupts, such as reset (dealt with as an interrupt assigned the highest priority), watchdog timer interrupt, etc. are regulated by hardware. figure 2.7.8 shows the priorities of hardware interrupts. software interrupts are not affected by the interrupt priority. if an instruction is executed, control branches invariably to the interrupt routine. (4) returning from an interrupt routine executing the reit instruction at the end of an interrupt routine returns the contents of the flag register (flg) as it was immediately before the start of interrupt sequence and the contents of the program counter (pc), both of which have been saved in the stack area. then control returns to the program that was being executed before the acceptance of the interrupt request, so that the suspended pro- cess resumes. return the other registers saved by software within the interrupt routine using the popm or similar instruction before executing the reit instruction. (6) interrupt resolution circuit when two or more interrupts are generated simultaneously, this circuit selects the interrupt with the highest priority level. figure 2.7.9 shows the circuit that judges the interrupt priority level. figure 2.7.8 hardware interrupts priorities _______ ________ reset > nmi > dbc > watchdog timer > peripheral i/o > single step > address match
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 55 rev. 1.0 M306H2MC-XXXFP figure 2.7.9 maskable interrupts priorities (peripheral i/o interrupts) timer b2 timer b0 timer a3 timer a1 timer b1 timer a4 timer a2 uart1 reception uart0 reception uart2 reception/ack a-d conversion dma1 bus collision detection timer a0 uart1 transmission uart0 transmission uart2 transmission/nack key input interrupt dma0 processor interrupt priority level (ipl) interrupt enable flag (i flag) int1 int2 int0 watchdog timer reset dbc nmi interrupt request accepted level 0 (initial value) priority level of each interrupt high low priority of peripheral i/o interrupts (if priority levels are same) timer b4 int3 timer b3 timer b5 serial i/o4/int5 serial i/o3/int4 address match interrupt request level judgment output to clock generating circuit (fig.2.5.3)
56 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP ______ 2.7.7 int interrupt ________ ________ int0 to int5 are triggered by the edges of external inputs. the edge polarity is selected using the polarity select bit. ________ of interrupt control registers, 0048 16 is used both as serial i/o4 and external interrupt int5 input ________ control register, and 0049 16 is used both as serial i/o3 and as external interrupt int4 input control register. use the interrupt request cause select bits - bits 6 and 7 of the interrupt request cause select register (035f 16 ) - to specify which interrupt request cause to select. after having set an interrupt request cause, be sure to clear the corresponding interrupt request bit before enabling an interrupt. either of the interrupt control registers - 0048 16 , 0049 16 - has the polarity-switching bit. be sure to set this bit to 0 to select an serial i/o as the interrupt request cause. as for external interrupt input, an interrupt can be generated both at the rising edge and at the falling edge by setting 1 in the inti interrupt polarity switching bit of the interrupt request cause select register (035f 16 ). to select both edges, set the polarity switching bit of the corresponding interrupt control register to falling edge ( 0 ). figure 2.7.10 shows the interrupt request cause select register. figure 2.7.10 interrupt request cause select register interrupt request cause select register bit name fumction bit symbol w r symbol address when reset ifsr 035f 16 00 16 ifsr0 b7 b6 b5 b4 b3 b2 b1 b0 aa aa a a aa aa a a int0 interrupt polarity swiching bit 0 : sio3 1 : int4 0 : sio4 1 : int5 0 : one edge 1 : two edges 0 : one edge 1 : two edges 0 : one edge 1 : two edges 0 : one edge 1 : two edges 0 : one edge 1 : two edges int1 interrupt polarity swiching bit int2 interrupt polarity swiching bit int3 interrupt polarity swiching bit int4 interrupt polarity swiching bit int5 interrupt polarity swiching bit 0 : one edge 1 : two edges interrupt request cause select bit interrupt request cause select bit ifsr1 ifsr2 ifsr3 ifsr4 ifsr5 ifsr6 ifsr7 aa aa a a aa aa a a aa a aa a aa a aa aa a a aa a aa a
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 57 rev. 1.0 M306H2MC-XXXFP interrupt control circuit key input interrupt control register (address 004d 16 ) key input interrupt request p10 7 /ki 3 p10 6 /ki 2 p10 5 /ki 1 p10 4 /ki 0 port p10 4 -p10 7 pull-up select bit port p10 7 direction register pull-up transistor port p10 7 direction register port p10 6 direction register port p10 5 direction register port p10 4 direction register pull-up transistor pull-up transistor pull-up transistor figure 2.7.11 block diagram of key input interrupt ______ 2.7.8 nmi interrupt ______ ______ ______ an nmi interrupt is generated when the input to the p8 5 /nmi pin changes from h to l . the nmi interrupt is a non-maskable external interrupt. the pin level can be checked in the port p8 5 register (bit 5 at address 03f0 16 ). this pin cannot be used as a normal port input. 2.7.9 key input interrupt if the direction register of any of p10 4 to p10 7 is set for input and a falling edge is input to that port, a key input interrupt is generated. a key input interrupt can also be used as a key-on wakeup function for cancelling the wait mode or stop mode. however, if you intend to use the key input interrupt, do not use p10 4 to p10 7 as a-d input ports. figure 2.7.11 shows the block diagram of the key input interrupt. note that if an l level is input to any pin that has not been disabled for input, inputs to the other pins are not detected as an interrupt.
58 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP 2.7.10 address match interrupt an address match interrupt is generated when the address match interrupt address register contents match the program counter value. two address match interrupts can be set, each of which can be enabled and disabled by an address match interrupt enable bit. address match interrupts are not affected by the interrupt enable flag (i flag) and processor interrupt priority level (ipl). the value of the program counter (pc) for an address match interrupt varies depending on the instruction being executed. note that when using the external data bus in width of 8 bits, the address match interrupt cannot be used for external area. figure 2.7.12 shows the address match interrupt-related registers. bit name bit symbol symbol address when reset aier 0009 16 xxxxxx00 2 address match interrupt enable register function w r aaaaaaaaaaaaaa a aaaaaaaaaaaa a aaaaaaaaaaaaaa aaaaaaaaaaaaaa a aaaaaaaaaaaa a aaaaaaaaaaaaaa address match interrupt 0 enable bit 0 : interrupt disabled 1 : interrupt enabled aier0 address match interrupt 1 enable bit aier1 aaaaaaaaaaaaaa aaaaaaaaaaaaaa symbol address when reset rmad0 0012 16 to 0010 16 x00000 16 rmad1 0016 16 to 0014 16 x00000 16 nothing is assigned. in an attempt to write to these bits, write 0 . the value, if read, turns out to be indeterminated. b7 b6 b5 b4 b3 b2 b1 b0 w r address setting register for address match interrupt function values that can be set address match interrupt register i (i = 0, 1) 00000 16 to fffff 16 nothing is assigned. in an attempt to write to these bits, write 0 . the value, if read, turns out to be indeterminated. 0 : interrupt disabled 1 : interrupt enabled b0 b7 b0 b3 (b19) (b16) b7 b0 (b15) (b8) b7 (b23) aa a aa a aa aa a a figure 2.7.12 address match interrupt-related registers
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 59 rev. 1.0 M306H2MC-XXXFP 2.7.11 precautions for interrupts (1) reading address 00000 16 when maskable interrupt is occurred, cpu read the interrupt information (the interrupt number and interrupt request level) in the interrupt sequence. the interrupt request bit of the certain interrupt written in address 00000 16 will then be set to 0 . reading address 00000 16 by software sets enabled highest priority interrupt source request bit to 0 . though the interrupt is generated, the interrupt routine may not be executed. do not read address 00000 16 by software. (2) setting the stack pointer the value of the stack pointer immediately after reset is initialized to 0000 16 . accepting an interrupt before setting a value in the stack pointer may become a factor of runaway. be sure to set a value in _______ the stack pointer before accepting an interrupt. when using the nmi interrupt, initialize the stack point at the beginning of a program. concerning the first instruction immediately after reset, gener- _______ ating any interrupts including the nmi interrupt is prohibited. _______ (3) the nmi interrupt _______ as for the nmi interrupt pin, an interrupt cannot be disabled. connect it to the vcc pin via a resistor (pull-up) if unused. be sure to work on it. _______ the nmi pin also serves as p8 5 , which is exclusively input. reading the contents of the p8 register allows reading the pin value. use the reading of this pin only for establishing the pin level at the time _______ when the nmi interrupt is input. _______ do not reset the cpu with the input to the nmi pin being in the l state. _______ do not attempt to go into stop mode with the input to the nmi pin being in the l state. with the input _______ to the nmi being in the l state, the cm10 is fixed to 0 , so attempting to go into stop mode is turned down. _______ do not attempt to go into wait mode with the input to the nmi pin being in the l state. with the input _______ to the nmi pin being in the l state, the cpu stops but the oscillation does not stop, so no power is saved. in this instance, the cpu is returned to the normal state by a later interrupt. _______ signals input to the nmi pin require an "l" level of 1 clock or more, from the operation clock of the cpu. (4) external interrupt ________ either an l level or an h level of at least 250 ns width is necessary for the signal input to pins int 0 ________ through int 5 regardless of the cpu operation clock. ________ ________ when the polarity of the int 0 to int 5 pins is changed, the interrupt request bit is sometimes set to "1". after changing the polarity, set the interrupt request bit to "0". figure 2.7.13 shows the proce- ______ dure for changing the int interrupt generate factor.
60 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP ______ figure 2.7.13 switching condition of int interrupt request example 1: int_switch1: fclr i ; disable interrupts. and.b #00h, 0055h ; clear ta0ic int. priority level and int. request bit. nop ; four nop instructions are required when using hold function. nop fset i ; enable interrupts. example 2: int_switch2: fclr i ; disable interrupts. and.b #00h, 0055h ; clear ta0ic int. priority level and int. request bit. mov.w mem, r0 ; dummy read. fset i ; enable interrupts. example 3: int_switch3: pushc flg ; push flag register onto stack fclr i ; disable interrupts. and.b #00h, 0055h ; clear ta0ic int. priority level and int. request bit. popc flg ; enable interrupts. the reason why two nop instructions (four when using the hold function) or dummy read are inserted before fset i in examples 1 and 2 is to prevent the interrupt enable flag i from being set before the interrupt control register is rewritten due to effects of the instruction queue. (5) rewrite the interrupt control register to rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register. if there is possibility of the interrupt request occur, rewrite the interrupt control register after the interrupt is disabled. the program examples are described as follow: set the polarity select bit clear the interrupt request bit to 0 set the interrupt priority level to level 1 to 7 (enable the accepting of inti interrupt request) set the interrupt priority level to level 0 (disable inti interrupt) clear the interrupt enable flag to 0 (disable interrupt) set the interrupt enable flag to 1 (enable interrupt) note:execute the setting above individually.don't execute two or more settings at once(by one instruction). when a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the interrupt request bit is not set sometimes even if the interrupt request for that register has been generated. this will depend on the instruction. if this creates problems, use the below instructions to change the register. instructions : and, or, bclr, bset
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 61 rev. 1.0 M306H2MC-XXXFP 2.8 watchdog timer the watchdog timer has the function of detecting when the program is out of control. the watchdog timer is a 15-bit counter which down-counts the clock derived by dividing the bclk using the prescaler. a watchdog timer interrupt is generated when an underflow occurs in the watchdog timer. when x in is selected for the bclk, bit 7 of the watchdog timer control register (address 000f 16 ) selects the prescaler division ratio (by 16 or by 128). when x cin is selected as the bclk, the prescaler is set for division by 2 regardless of bit 7 of the watchdog timer control register (address 000f 16 ). thus the watchdog timer's period can be calculated as given below. the watchdog timer's period is, however, subject to an error due to the pre-scaler. bclk write to the watchdog timer start register (address 000e 16 ) reset watchdog timer interrupt request watchdog timer set to ?fff 16 1/128 1/16 ?m07 = 0 ?dc7 = 1 ?m07 = 0 ?dc7 = 0 ?m07 = 1 hold 1/2 prescaler for example, suppose that bclk runs at 10 mhz and that 16 has been chosen for the dividing ratio of the pre-scaler, then the watchdog timer's period becomes approximately 52.4 ms. the watchdog timer is initialized by writing to the watchdog timer start register (address 000e 16 ) and when a watchdog timer interrupt request is generated. the prescaler is initialized only when the micro- computer is reset. after a reset is cancelled, the watchdog timer and prescaler are both stopped. the count is started by writing to the watchdog timer start register (address 000e 16 ). figure 2.8.1 shows the block diagram of the watchdog timer. figure 2.8.2 shows the watchdog timer- related registers. with x in chosen for bclk watchdog timer period = pre-scaler dividing ratio (16 or 128) x watchdog timer count (32768) bclk with x cin chosen for bclk watchdog timer period = pre-scaler dividing ratio (2) x watchdog timer count (32768) bclk figure 2.8.1 block diagram of watchdog timer
62 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP watchdog timer control register symbol address when reset wdc 000f 16 000xxxxx 2 function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 high-order bit of watchdog timer wdc7 bit name prescaler select bit 0 : divided by 16 1 : divided by 128 watchdog timer start register symbol address when reset wdts 000e 16 indeterminate w r b7 b0 function the watchdog timer is initialized and starts counting after a write instruction to this register. the watchdog timer value is always initialized to 7fff 16 regardless of whatever value is written. reserved bit reserved bit must always be set to 0 must always be set to 0 0 0 aa aa a aa a aa a a figure 2.8.2 watchdog timer control and start registers
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 63 rev. 1.0 M306H2MC-XXXFP figure 2.9.1 block diagram of dmac a a a a a a a aa aa aa aa a a aa aa aa aa aa a a a a a a data bus low-order bits dma latch high-order bits dma latch low-order bits dma0 source pointer sar0(20) dma0 destination pointer dar0 (20) dma0 forward address pointer (20) (note) data bus high-order bits aa aa aa a a aa aa aaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaaa aaaaaaa address bus a a a a aa aa aa aa dma1 destination pointer dar1 (20) dma1 source pointer sar1 (20) dma1 forward address pointer (20) (note) aa aa aa dma0 transfer counter reload register tcr0 (16) dma0 transfer counter tcr0 (16) dma1 transfer counter reload register tcr1 (16) dma1 transfer counter tcr1 (16) a a a (addresses 0029 16 , 0028 16 ) (addresses 0039 16 , 0038 16 ) (addresses 0022 16 to 0020 16 ) (addresses 0026 16 to 0024 16 ) (addresses 0032 16 to 0030 16 ) (addresses 0036 16 to 0034 16 ) note: pointer is incremented by a dma request. aa aa aa aa aa aa a a a a a a a a a a a a aa aa aa aa a a a a a a a a a a either a write signal to the software dma request bit or an interrupt request signal is used as a dma transfer request signal. but the dma transfer is affected neither by the interrupt enable flag (i flag) nor by the interrupt priority level. the dma transfer doesn't affect any interrupts either. if the dmac is active (the dma enable bit is set to 1), data transfer starts every time a dma transfer request signal occurs. if the cycle of the occurrences of dma transfer request signals is higher than the dma transfer cycle, there can be instances in which the number of transfer requests doesn't agree with the number of transfers. for details, see the description of the dma request bit. 2.9 dmac this microcomputer has two dmac (direct memory access controller) channels that allow data to be sent to memory without using the cpu. dmac shares the same data bus with the cpu. the dmac is given a higher right of using the bus than the cpu, which leads to working the cycle stealing method. on this account, the operation from the occurrence of dma transfer request signal to the completion of 1-word (16-bit) or 1-byte (8-bit) data transfer can be performed at high speed. figure 2.9.1 shows the block diagram of the dmac. table 2.9.1 shows the dmac specifications. figures 2.9.2 to 2.9.4 show the registers used by the dmac.
64 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP table 2.9.1 dmac specifications note: dma transfer is not effective to any interrupt. dma transfer is affected neither by the interrupt enable flag (i flag) nor by the interrupt priority level. forward address pointer and reload timing for transfer counter item specification no. of channels 2 (cycle steal method) transfer memory space from any address in the 1m bytes space to a fixed address from a fixed address to any address in the 1m bytes space from a fixed address to a fixed address (note that dma-related registers [0020 16 to 003f 16 ] cannot be accessed) maximum no. of bytes transferred 128k bytes (with 16-bit transfers) or 64k bytes (with 8-bit transfers) dma request factors (note) ________ ________ ________ ________ falling edge of int0 or int1 (int0 can be selected by dma0, int1 by dma1) or both edge timer a0 to timer a4 interrupt requests timer b0 to timer b5 interrupt requests uart0 transfer and reception interrupt requests uart1 transfer and reception interrupt requests uart2 transfer and reception interrupt requests serial i/o3, 4 interrpt requests a-d conversion interrupt requests software triggers channel priority dma0 takes precedence if dma0 and dma1 requests are generated simultaneously transfer unit 8 bits or 16 bits transfer address direction forward/fixed (forward direction cannot be specified for both source and destination simultaneously) transfer mode single transfer mode after the transfer counter underflows, the dma enable bit turns to ?? and the dmac turns inactive repeat transfer mode after the transfer counter underflows, the value of the transfer counter reload register is reloaded to the transfer counter. the dmac remains active unless a ? is written to the dma enable bit. dma interrupt request generation timing when an underflow occurs in the transfer counter active when the dma enable bit is set to ?? the dmac is active. when the dmac is active, data transfer starts every time a dma transfer request signal occurs. inactive ?hen the dma enable bit is set to ?? the dmac is inactive. after the transfer counter underflows in single transfer mode at the time of starting data transfer immediately after turning the dmac active, the value of one of source pointer and destination pointer - the one specified for the forward direction - is reloaded to the forward direction address pointer,and the value of the transfer counter reload register is reloaded to the transfer counter. writing to register registers specified for forward direction transfer are always write enabled. registers specified for fixed address transfer are write-enabled when the dma enable bit is ?? reading the register can be read at any time. however, when the dma enable bit is ?? reading the register set up as the forward register is the same as reading the value of the forward address pointer.
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 65 rev. 1.0 M306H2MC-XXXFP dma0 request cause select register symbol address when reset dm0sl 03b8 16 00 16 function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 dma request cause select bit dsel0 rw dsel1 dsel2 dsel3 nothing is assigned. in an attempt to write to these bits, write 0 . the value, if read, turns out to be 0 . software dma request bit if software trigger is selected, a dma request is generated by setting this bit to 1 (when read, the value of this bit is always 0 ) dsr b3 b2 b1 b0 0 0 0 0 : falling edge of int0 pin 0 0 0 1 : software trigger 0 0 1 0 : timer a0 0 0 1 1 : timer a1 0 1 0 0 : timer a2 0 1 0 1 : timer a3 0 1 1 0 : timer a4 (dms=0) /two edges of int0 pin (dms=1) 0 1 1 1 : timer b0 (dms=0) timer b3 (dms=1) 1 0 0 0 : timer b1 (dms=0) timer b4 (dms=1) 1 0 0 1 : timer b2 (dms=0) timer b5 (dms=1) 1 0 1 0 : uart0 transmit 1 0 1 1 : uart0 receive 1 1 0 0 : uart2 transmit 1 1 0 1 : uart2 receive 1 1 1 0 : a-d conversion 1 1 1 1 : uart1 transmit aa a aa a aa a aa aa a a aa aa a a bit name dma request cause expansion bit dms 0 : normal 1 : expanded cause aa a figure 2.9.2 dmac register (1)
66 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP dmai control register symbol address when reset dmicon(i=0,1) 002c 16 , 003c 16 00000x00 2 bit name function bit symbol transfer unit bit select bit b7 b6 b5 b4 b3 b2 b1 b0 0 : 16 bits 1 : 8 bits dmbit rw dmasl dmas dmae repeat transfer mode select bit 0 : single transfer 1 : repeat transfer dma request bit (note 1) 0 : dma not requested 1 : dma requested 0 : disabled 1 : enabled 0 : fixed 1 : forward dma enable bit source address direction select bit (note 3) destination address direction select bit (note 3) 0 : fixed 1 : forward dsd dad nothing is assigned. in an attempt to write to these bits, write 0 . the value, if read, turns out to be 0 . note 1: dma request can be cleared by resetting the bit. note 2: this bit can only be set to 0 . note 3: source address direction select bit and destination address direction select bit cannot be set to 1 simultaneously. (note 2) aa a aa a aa a aa a aa a aa aa a a dma1 request cause select register symbol address when reset dm1sl 03ba 16 00 16 function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 dma request cause select bit dsel0 rw dsel1 dsel2 dsel3 nothing is assigned. in an attempt to write to these bits, write 0 . the value, if read, turns out to be 0 . software dma request bit if software trigger is selected, a dma request is generated by setting this bit to 1 (when read, the value of this bit is always 0 ) dsr b3 b2 b1 b0 0 0 0 0 : falling edge of int1 pin 0 0 0 1 : software trigger 0 0 1 0 : timer a0 0 0 1 1 : timer a1 0 1 0 0 : timer a2 0 1 0 1 : timer a3(dms=0) /serial i/o3 (dms=1) 0 1 1 0 : timer a4 (dms=0) /serial i/o4 (dms=1) 0 1 1 1 : timer b0 (dms=0) /two edges of int1 (dms=1) 1 0 0 0 : timer b1 1 0 0 1 : timer b2 1 0 1 0 : uart0 transmit 1 0 1 1 : uart0 receive 1 1 0 0 : uart2 transmit 1 1 0 1 : uart2 receive 1 1 1 0 : a-d conversion 1 1 1 1 : uart1 receive a a aa aa a aa a aa a aa a a aa aa bit name dma request cause expansion bit dms 0 : normal 1 : expanded cause a aa figure 2.9.3 dmac register (2)
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 67 rev. 1.0 M306H2MC-XXXFP b7 b0 b7 b0 (b8) (b15) function rw transfer counter set a value one less than the transfer count symbol address when reset tcr0 0029 16 , 0028 16 indeterminate tcr1 0039 16 , 0038 16 indeterminate dmai transfer counter (i = 0, 1) transfer count specification 0000 16 to ffff 16 b7 (b23) b3 b0 b7 b0 b7 b0 (b8) (b16)(b15) (b19) function rw source pointer stores the source address symbol address when reset sar0 0022 16 to 0020 16 indeterminate sar1 0032 16 to 0030 16 indeterminate dmai source pointer (i = 0, 1) transfer count specification 00000 16 to fffff 16 nothing is assigned. in an attempt to write to these bits, write 0 . the value, if read, turns out to be 0 . symbol address when reset dar0 0026 16 to 0024 16 indeterminate dar1 0036 16 to 0034 16 indeterminate b3 b0 b7 b0 b7 b0 (b8) (b15) (b16) (b19) function rw destination pointer stores the destination address dmai destination pointer (i = 0, 1) transfer count specification 00000 16 to fffff 16 b7 (b23) nothing is assigned. in an attempt to write to these bits, write 0 . the value, if read, turns out to be 0 . a aa a aa a aa figure 2.9.4 dmac register (3)
68 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP (1) transfer cycle the transfer cycle consists of the bus cycle in which data is read from memory or from the sfr area (source read) and the bus cycle in which the data is written to memory or to the sfr area (destination write). the number of read and write bus cycles depends on the source and destination addresses and, the level of the byte pin. in memory expansion mode and microprocessor mode, the number of read and write bus cycles also depends on the level of the byte pin. also, the bus cycle itself is longer when software waits are inserted. (a) effect of source and destination addresses when 16-bit data is transferred on a 16-bit data bus, and the source and destination both start at odd addresses, there are one more source read cycle and destination write cycle than when the source and destination both start at even addresses. (b) effect of byte pin level when transferring 16-bit data over an 8-bit data bus (byte pin = h ) in memory expansion mode and microprocessor mode, the 16 bits of data are sent in two 8-bit blocks. therefore, two bus cycles are required for reading the data and two are required for writing the data. also, in contrast to when the cpu accesses internal memory, when the dmac accesses internal memory (internal ram, and sfr), these areas are accessed using the data size selected by the byte pin. (c) effect of software wait when the sfr area or a memory area with a software wait is accessed, the number of cycles is increased for the wait by 1 bus cycle. the length of the cycle is determined by bclk. figure 2.9.5 shows the example of the transfer cycles for a source read. for convenience, the destination write cycle is shown as one cycle and the source read cycles for the different conditions are shown. in reality, the destination write cycle is subject to the same conditions as the source read cycle, with the transfer cycle changing accordingly. when calculating the transfer cycle, remember to apply the respec- tive conditions to both the destination write cycle and the source read cycle. for example (2) in figure 2.9.5, if data is being transferred in 16-bit units on an 8-bit bus, two bus cycles are required for both the source read cycle and the destination write cycle.
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 69 rev. 1.0 M306H2MC-XXXFP bclk address bus rd signal wr signal data bus cpu use cpu use cpu use cpu use source source destination destination dummy cycle dummy cycle (1) 8-bit transfers 16-bit transfers from even address and the source address is even. bclk address bus rd signal wr signal data bus cpu use cpu use cpu use cpu use source source destination destination dummy cycle dummy cycle (3) one wait is inserted into the source read under the conditions in (1) bclk address bus rd signal wr signal data bus cpu use cpu use cpu use cpu use source source destination destination dummy cycle dummy cycle source + 1 source + 1 (2) 16-bit transfers and the source address is odd transferring 16-bit data on an 8-bit data bus (in this case, there are also two destination write cycles). bclk address bus rd signal wr signal data bus cpu use cpu use cpu use cpu use source source destination destination dummy cycle dummy cycle source + 1 source + 1 (4) one wait is inserted into the source read under the conditions in (2) (when 16-bit data is transferred on an 8-bit data bus, there are two destination write cycles). note: the same timing changes occur with the respective conditions at the destination as at the source. figure 2.9.5 example of the transfer cycles for a source read
70 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP 16-bit even 1 1 1 1 8-bit transfers (byte= l ) odd 1 1 1 1 (dmbit= 1 ) 8-bit even 11 (byte = h ) odd 11 16-bit even 1 1 1 1 16-bit transfers (byte = l ) odd 2 2 2 2 (dmbit= 0 ) 8-bit even 22 (byte = h ) odd 22 table 2.9.2 no. of dmac transfer cycles internal memory external memory internal rom/ram internal rom/ram sfr area separate bus separate bus multiplex no wait with wait no wait with wait bus 122123 coefficient j, k transfer unit bus width access address memory expansion mode microprocessor mode no. of read no. of write cycles cycles single-chip mode no. of read no. of write cycles cycles (2) dmac transfer cycles any combination of even or odd transfer read and write addresses is possible. table 2.9.2 shows the number of dmac transfer cycles. the number of dmac transfer cycles can be calculated as follows: no. of transfer cycles per transfer unit = no. of read cycles x j + no. of write cycles x k
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 71 rev. 1.0 M306H2MC-XXXFP 2.9.1 dma enable bit setting the dma enable bit to "1" makes the dmac active. the dmac carries out the following opera- tions at the time data transfer starts immediately after dmac is turned active. (1) reloads the value of one of the source pointer and the destination pointer - the one specified for the forward direction - to the forward direction address pointer. (2) reloads the value of the transfer counter reload register to the transfer counter. thus overwriting "1" to the dma enable bit with the dmac being active carries out the operations given above, so the dmac operates again from the initial state at the instant "1" is overwritten to the dma enable bit. 2.9.2 dma request bit the dmac can generate a dma transfer request signal triggered by a factor chosen in advance out of dma request factors for each channel. dma request factors include the following. * factors effected by using the interrupt request signals from the built-in peripheral functions and software dma factors (internal factors) effected by a program. * external factors effected by utilizing the input from external interrupt signals. for the selection of dma request factors, see the descriptions of the dmai factor selection register. the dma request bit turns to "1" if the dma transfer request signal occurs regardless of the dmac's state (regardless of whether the dma enable bit is set "1" or to "0"). it turns to "0" immediately before data transfer starts. in addition, it can be set to "0" by use of a program, but cannot be set to "1". there can be instances in which a change in dma request factor selection bit causes the dma re- quest bit to turn to "1". so be sure to set the dma request bit to "0" after the dma request factor selection bit is changed. the dma request bit turns to "1" if a dma transfer request signal occurs, and turns to "0" immediately before data transfer starts. if the dmac is active, data transfer starts immediately, so the value of the dma request bit, if read by use of a program, turns out to be "0" in most cases. to examine whether the dmac is active, read the dma enable bit. here follows the timing of changes in the dma request bit. (1) internal factors except the dma request factors triggered by software, the timing for the dma request bit to turn to "1" due to an internal factor is the same as the timing for the interrupt request bit of the interrupt control register to turn to "1" due to several factors. turning the dma request bit to "1" due to an internal factor is timed to be effected immediately before the transfer starts. (2) external factors an external factor is a factor caused to occur by the leading edge of input from the inti pin (i depends on which dmac channel is used). selecting the inti pins as external factors using the dma request factor selection bit causes input from these pins to become the dma transfer request signals. the timing for the dma request bit to turn to "1" when an external factor is selected synchronizes with the signal's edge applicable to the function specified by the dma request factor selection bit (synchro- nizes with the trailing edge of the input signal to each inti pin, for example). with an external factor selected, the dma request bit is timed to turn to "0" immediately before data transfer starts similarly to the state in which an internal factor is selected.
72 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP (3) the priorities of channels and dma transfer timing if a dma transfer request signal falls on a single sampling cycle (a sampling cycle means one period from the leading edge to the trailing edge of bclk), the dma request bits of applicable channels concurrently turn to "1". if the channels are active at that moment, dma0 is given a high priority to start data transfer. when dma0 finishes data transfer, it gives the bus right to the cpu. when the cpu finishes single bus access, then dma1 starts data transfer and gives the bus right to the cpu. an example in which dma transfer is carried out in minimum cycles at the time when dma transfer request signals due to external factors concurrently occur. figure 2.9.6 an example of dma transfer effected by external factors. bclk aaaa aaaa dma0 aaaa aaaa dma1 dma0 request bit dma1 request bit aa aaaaa a a aaaaa aa cpu int0 int1 obtainm ent of the bus right an example in which dma transmission is carried out in minimum cycles at the time when dma transmission request signals due to external factors concurrently occur. figure 2.9.6 an example of dma transfer effected by external factors
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 73 rev. 1.0 M306H2MC-XXXFP ?timer mode ?one-shot mode ?pwm mode ?timer mode ?one-shot mode ?pwm mode ?timer mode ?one-shot mode ?pwm mode ?timer mode ?one-shot mode ?pwm mode ?timer mode ?one-shot mode ?pwm mode ?event counter mode ?event counter mode ?event counter mode ?event counter mode ?event counter mode ta0 in ta1 in ta2 in ta3 in ta4 in timer a0 timer a1 timer a2 timer a3 timer a4 f 1 f 8 f 32 f c32 timer a0 interrupt timer a1 interrupt timer a2 interrupt timer a3 interrupt timer a4 interrupt noise filter noise filter noise filter noise filter noise filter 1/32 f c32 1/8 1/4 f 1 f 8 f 32 x in x cin clock prescaler reset flag (bit 7 at address 0381 16 ) set to ? reset clock prescaler timer b2 overflow note 1: the ta0 in pin (p7 1 ) is shared with rxd 2 and the tb5 in pin, so be careful. figure 2.10.1 timer a block diagram 2.10 timer there are eleven 16-bit timers. these timers can be classified by function into timers a (five) and timers b (six). all these timers function independently. figures 2.10.1 and 2.10.2 show the block diagram of timers.
74 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP figure 2.10.2 timer b block diagram event counter mode event counter mode event counter mode timer mode pulse width measuring mode timer mode pulse width measuring mode timer mode pulse width measuring mode tb0 in tb1 in tb2 in timer b0 timer b1 timer b2 f 1 f 8 f 32 f c32 timer b0 interrupt noise filter noise filter noise filter 1/32 f c32 1/8 1/4 f 1 f 8 f 32 x in x cin clock prescaler reset flag (bit 7 at address 0381 16 ) set to 1 reset clock prescaler timer a event counter mode event counter mode event counter mode timer mode pulse width measuring mode timer mode pulse width measuring mode timer mode pulse width measuring mode tb3 in tb4 in tb5 in timer b3 timer b4 timer b5 timer b3 interrupt noise filter noise filter noise filter timer b1 interrupt timer b2 interrupt timer b4 interrupt timer b5 interrupt note 1: the tb5 in pin (p7 1 ) is shared with rxd 2 and the ta0 in pin, so be careful.
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 75 rev. 1.0 M306H2MC-XXXFP t i m e r a i m o d e r e g i s t e r s y m b o la d d r e s sw h e n r e s e t t a i m r ( i = 0 t o 4 )0 3 9 6 1 6 t o 0 3 9 a 1 6 0 0 1 6 b i t n a m ef u n c t i o n b i t s y m b o l w r b 7b 6b 5b 4b 3b 2b 1b 0 0 0 : t i m e r m o d e 0 1 : e v e n t c o u n t e r m o d e 1 0 : o n e - s h o t t i m e r m o d e 1 1 : p u l s e w i d t h m o d u l a t i o n ( p w m ) m o d e b 1 b 0 t c k 1 m r 3 m r 2 m r 1 t m o d 1 m r 0 t m o d 0 t c k 0 f u n c t i o n v a r i e s w i t h e a c h o p e r a t i o n m o d e c o u n t s o u r c e s e l e c t b i t ( f u n c t i o n v a r i e s w i t h e a c h o p e r a t i o n m o d e ) o p e r a t i o n m o d e s e l e c t b i t figure 2.10.3 block diagram of timer a figure 2.10.4 timer a-related registers (1) c o u n t s t a r t f l a g ( a d d r e s s 0 3 8 0 1 6 ) u p c o u n t / d o w n c o u n t t a ia d d r e s s e st a jt a k t i m e r a 00 3 8 7 1 6 0 3 8 6 1 6 t i m e r a 4t i m e r a 1 t i m e r a 10 3 8 9 1 6 0 3 8 8 1 6 t i m e r a 0t i m e r a 2 t i m e r a 20 3 8 b 1 6 0 3 8 a 1 6 t i m e r a 1t i m e r a 3 t i m e r a 30 3 8 d 1 6 0 3 8 c 1 6 t i m e r a 2t i m e r a 4 t i m e r a 4 0 3 8 f 1 6 0 3 8 e 1 6 t i m e r a 3t i m e r a 0 a l w a y s d o w n c o u n t e x c e p t i n e v e n t c o u n t e r m o d e r e l o a d r e g i s t e r ( 1 6 ) c o u n t e r ( 1 6 ) l o w - o r d e r 8 b i t s h i g h - o r d e r 8 b i t s c l o c k s o u r c e s e l e c t i o n t i m e r ( g a t e f u n c t i o n ) t i m e r o n e s h o t p w m f 1 f 8 f 3 2 e x t e r n a l t r i g g e r t a i i n ( i = 0 t o 4 ) t b 2 o v e r f l o w e v e n t c o u n t e r f c 3 2 c l o c k s e l e c t i o n t a j o v e r f l o w ( j = i 1 . n o t e , h o w e v e r , t h a t j = 4 w h e n i = 0 ) p u l s e o u t p u t t o g g l e f l i p - f l o p t a i o u t ( i = 0 t o 4 ) d a t a b u s l o w - o r d e r b i t s d a t a b u s h i g h - o r d e r b i t s u p / d o w n f l a g d o w n c o u n t ( a d d r e s s 0 3 8 4 1 6 ) t a k o v e r f l o w ( k = i + 1 . n o t e , h o w e v e r , t h a t k = 0 w h e n i = 4 ) p o l a r i t y s e l e c t i o n 2.10.1 timer a figure 2.10.3 shows the block diagram of timer a. figures 2.10.4 to 2.10.6 show the timer a-related registers. except in event counter mode, timers a0 through a4 all have the same function. use the timer ai mode register (i = 0 to 4) bits 0 and 1 to choose the desired mode. timer a has the four operation modes listed as follows: timer mode: the timer counts an internal count source. event counter mode: the timer counts pulses from an external source or a timer over flow. one-shot timer mode: the timer stops counting when the count reaches 0000 16 . pulse width modulation (pwm) mode: the timer outputs pulses of a given width.
76 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP figure 2.10.5 timer a-related registers (2) t i m e r a 4 u p / d o w n f l a g t i m e r a 3 u p / d o w n f l a g t i m e r a 2 u p / d o w n f l a g t i m e r a 1 u p / d o w n f l a g t i m e r a 0 u p / d o w n f l a g t i m e r a 2 t w o - p h a s e p u l s e s i g n a l p r o c e s s i n g s e l e c t b i t t i m e r a 3 t w o - p h a s e p u l s e s i g n a l p r o c e s s i n g s e l e c t b i t t i m e r a 4 t w o - p h a s e p u l s e s i g n a l p r o c e s s i n g s e l e c t b i t s y m b o l a d d r e s s w h e n r e s e t u d f 0 3 8 4 1 6 0 0 1 6 t a 4 p t a 3 p t a 2 p u p / d o w n f l a g ( n o t e 1 ) b i t n a m ef u n c t i o n b i t s y m b o l w r b 7b 6b 5b 4b 3b 2b 1b 0 t a 4 u d t a 3 u d t a 2 u d t a 1 u d t a 0 u d 0 : d o w n c o u n t 1 : u p c o u n t t h i s s p e c i f i c a t i o n b e c o m e s v a l i d w h e n t h e u p / d o w n f l a g c o n t e n t i s s e l e c t e d f o r u p / d o w n s w i t c h i n g c a u s e 0 : t w o - p h a s e p u l s e s i g n a l p r o c e s s i n g d i s a b l e d 1 : t w o - p h a s e p u l s e s i g n a l p r o c e s s i n g e n a b l e d w h e n n o t u s i n g t h e t w o - p h a s e p u l s e s i g n a l p r o c e s s i n g f u n c t i o n , s e t t h e s e l e c t b i t t o 0 s y m b o l a d d r e s s w h e n r e s e t t a b s r 0 3 8 0 1 6 0 0 1 6 c o u n t s t a r t f l a g b i t n a m ef u n c t i o n b i t s y m b o l w r b 7b 6b 5b 4b 3b 2b 1b 0 t i m e r b 2 c o u n t s t a r t f l a g t i m e r b 1 c o u n t s t a r t f l a g t i m e r b 0 c o u n t s t a r t f l a g t i m e r a 4 c o u n t s t a r t f l a g t i m e r a 3 c o u n t s t a r t f l a g t i m e r a 2 c o u n t s t a r t f l a g t i m e r a 1 c o u n t s t a r t f l a g t i m e r a 0 c o u n t s t a r t f l a g 0 : s t o p s c o u n t i n g 1 : s t a r t s c o u n t i n g t b 2 s t b 1 s t b 0 s t a 4 s t a 3 s t a 2 s t a 1 s t a 0 s s y m b o l a d d r e s s w h e n r e s e t t a 0 0 3 8 7 1 6 , 0 3 8 6 1 6 i n d e t e r m i n a t e t a 1 0 3 8 9 1 6 , 0 3 8 8 1 6 i n d e t e r m i n a t e t a 2 0 3 8 b 1 6 , 0 3 8 a 1 6 i n d e t e r m i n a t e t a 3 0 3 8 d 1 6 , 0 3 8 c 1 6 i n d e t e r m i n a t e t a 4 0 3 8 f 1 6 , 0 3 8 e 1 6 i n d e t e r m i n a t e b 7b 0b 7b 0 ( b 1 5 )( b 8 ) t i m e r a i r e g i s t e r ( n o t e 1 ) w r t i m e r m o d e 0 0 0 0 1 6 t o f f f f 1 6 c o u n t s a n i n t e r n a l c o u n t s o u r c e f u n c t i o n v a l u e s t h a t c a n b e s e t e v e n t c o u n t e r m o d e 0 0 0 0 1 6 t o f f f f 1 6 c o u n t s p u l s e s f r o m a n e x t e r n a l s o u r c e o r t i m e r o v e r f l o w ( n o t e 2 , 4 ) o n e - s h o t t i m e r m o d e 0 0 0 0 1 6 t o f f f f 1 6 c o u n t s a o n e s h o t w i d t h ( n o t e 3 , 4 ) p u l s e w i d t h m o d u l a t i o n m o d e ( 1 6 - b i t p w m ) f u n c t i o n s a s a 1 6 - b i t p u l s e w i d t h m o d u l a t o r p u l s e w i d t h m o d u l a t i o n m o d e ( 8 - b i t p w m ) t i m e r l o w - o r d e r a d d r e s s f u n c t i o n s a s a n 8 - b i t p r e s c a l e r a n d h i g h - o r d e r a d d r e s s f u n c t i o n s a s a n 8 - b i t p u l s e w i d t h m o d u l a t o r 0 0 1 6 ~ f e 1 6 (high-order address) 00 16 ~ f f 16 (low-order address) ( n o t e 3 , 4 ) 0 0 0 0 1 6 t o f f f e 1 6 n o t e 1 : r e a d a n d w r i t e d a t a i n 1 6 - b i t u n i t s . n o t e 2 : w h e n t h e t i m e r a i r e g i s t e r i s s e t t o 0 0 0 0 1 6 , t h e c o u n t e r d o e s n o t o p e r a t e a n d t h e t i m e r a i i n t e r r u p t r e q u e s t i s n o t g e n e r a t e d . w h e n t h e p u l s e i s s e t t o o u t p u t , t h e p u l s e d o e s n o t o u t p u t f r o m t h e t a i o u t p i n . n o t e 3 : w h e n t h e t i m e r a i r e g i s t e r i s s e t t o 0 0 0 0 1 6 , t h e p u l s e w i d t h m o d u l a t o r d o e s n o t o p e r a t e a n d t h e o u t p u t l e v e l o f t h e t a i o u t p i n r e m a i n s l l e v e l , , t h e r e f o r e t h e t i m e r a i i n t e r r u p t r e q u e s t i s n o t g e n e r a t e d . t h i s a l s o o c c u r s i n t h e 8 - b i t p u l s e w i d t h m o d u l a t o r m o d e w h e n t h e s i g n i f i c a n t 8 h i g h - o r d e r b i t s i n t h e t i m e r a i r e g i s t e r a r e s e t t o 0 0 1 6 . n o t e 4 : u s e m o v i n s t r u c t i o n t o w r i t e t o t h i s r e g i s t e r . n o t e 5 : i n t h e c a s e o f u s i n g e v e n t c o u n t e r m o d e a s f r e e - r u n t y p e , t h e t i m e r r e g i s t e r c o n t e n t s m a y b e u n k o w n w h e n c o u n t i n g b e g i n s . ( r e f e r 3 . u s a g e p r e c a u t i o n . ) n o t e 1 : u s e m o v i n s t r u c t i o n t o w r i t e t o t h i s r e g i s t e r . n o t e 2 : s e t t h e t a i i n a n d t a i o u t p i n s c o r r e s p o n d e n t p o r t d i r e c t i o n r e g i s t e r s t o 0 .
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 77 rev. 1.0 M306H2MC-XXXFP symbol address when reset cpsrf 0381 16 0xxxxxxx 2 clock prescaler reset flag bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa clock prescaler reset flag 0 : no effect 1 : prescaler is reset (when read, the value is 0 ) cpsr w r nothing is assigned. in an attempt to write to these bits, write 0 . the value, if read, turns out to be indeterminate. ta1tgl symbol address when reset trgsr 0383 16 00 16 timer a1 event/trigger select bit 0 0 : input on ta1 in is selected (note) 0 1 : tb2 overflow is selected 1 0 : ta0 overflow is selected 1 1 : ta2 overflow is selected trigger select register bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 0 0 : input on ta2 in is selected (note) 0 1 : tb2 overflow is selected 1 0 : ta1 overflow is selected 1 1 : ta3 overflow is selected 0 0 : input on ta3 in is selected (note) 0 1 : tb2 overflow is selected 1 0 : ta2 overflow is selected 1 1 : ta4 overflow is selected 0 0 : input on ta4 in is selected (note) 0 1 : tb2 overflow is selected 1 0 : ta3 overflow is selected 1 1 : ta0 overflow is selected timer a2 event/trigger select bit timer a3 event/trigger select bit timer a4 event/trigger select bit w r ta1tgh ta2tgl ta2tgh ta3tgl ta3tgh ta4tgl ta4tgh b1 b0 b3 b2 b5 b4 b7 b6 note: set the corresponding port direction register to 0 . ta1os ta2os ta0os one-shot start flag symbol address when reset onsf 0382 16 00x00000 2 timer a0 one-shot start flag timer a1 one-shot start flag timer a2 one-shot start flag timer a3 one-shot start flag timer a4 one-shot start flag ta3os ta4os bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 nothing is assigned. in an attempt to write to this bit, write 0 . the value, if read, turns out to be indeterminate. ta0tgl ta0tgh 0 0 : input on ta0 in is selected (note) 0 1 : tb2 overflow is selected 1 0 : ta4 overflow is selected 1 1 : ta1 overflow is selected timer a0 event/trigger select bit b7 b6 note: set the corresponding port direction register to 0 . w r 1 : timer start when read, the value is 0 a aa a a aa aa a aa a aa a a aa aa a a aa aa a aa a a aa aa a aa a aa a aa a aa a aa a aa a aa a a aa aa a a aa aa a a aa aa figure 2.10.6 timer a-related registers (3)
78 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP item specification count source f 1 , f 8 , f 32 , f c32 count operation down count when the timer underflows, it reloads the reload register contents before continuing counting divide ratio 1/(n+1) n : set value count start condition count start flag is set (= 1) count stop condition count start flag is reset (= 0) interrupt request generation timing when the timer underflows tai in pin function programmable i/o port or gate input tai out pin function programmable i/o port or pulse output read from timer count value can be read out by reading timer ai register write to timer when counting stopped when a value is written to timer ai register, it is written to both reload register and counter when counting in progress when a value is written to timer ai register, it is written to only reload register (transferred to counter at next reload time) select function gate function counting can be started and stopped by the tai in pin s input signal pulse output function each time the timer underflows, the tai out pin s polarity is reversed note 1: the settings of the corresponding port register and port direction register are invalid. note 2: the bit can be 0 or 1 . note 3: set the corresponding port direction register to 0 . timer ai mode register symbol address when reset taimr(i=0 to 4) 0396 16 to 039a 16 00 16 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 0 0 : timer mode b1 b0 tmod1 tmod0 mr0 pulse output function select bit 0 : pulse is not output (ta iout pin is a normal port pin) 1 : pulse is output (note 1) (ta iout pin is a pulse output pin) gate function select bit 0 x (note 2) : gate function not available (tai in pin is a normal port pin) 1 0 : timer counts only when ta iin pin is held l (note 3) 1 1 : timer counts only when ta iin pin is held h (note 3) b4 b3 mr2 mr1 mr3 0 (must always be fixed to 0 in timer mode) 0 0 : f 1 0 1 : f 8 1 0 : f 32 1 1 : f c32 b7 b6 tck1 tck0 count source select bit 00 0 a a a a a a a a a a a a a a a a a a a a a a a a table 2.10.1 specifications of timer mode (1) timer mode in this mode, the timer counts an internally generated count source. (see table 2.10.1) figure 2.10.7 shows the timer ai mode register in timer mode. figure 2.10.7 timer ai mode register in timer mode
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 79 rev. 1.0 M306H2MC-XXXFP timer ai mode register note 1: in event counter mode, the count source is selected by the event / trigger select bit (addresses 0382 16 and 0383 16 ). note 2: the settings of the corresponding port register and port direction register are invalid. note 3: valid only when counting an external signal. note 4: when an l signal is input to the tai out pin, the downcount is activated. when h , the upcount is activated. set the corresponding port direction register to 0 . note 5: in the case of using event counter mode as free-run type , the timer register contents may be unkown when counting begins.(refer 3. usage precaution.) symbol address when reset taimr(i = 0, 1) 0396 16 , 0397 16 00 16 w r b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 0 1 : event counter mode (note 1) b1 b0 tmod0 mr0 pulse output function select bit 0 : pulse is not output (ta iout pin is a normal port pin) 1 : pulse is output (note 2) (ta iout pin is a pulse output pin) count polarity select bit (note 3) mr2 mr1 mr3 0 (must always be fixed to 0 in event counter mode) tck0 count operation type select bit 01 0 0 : counts external signal's falling edge 1 : counts external signal's rising edge up/down switching cause select bit 0 : up/down flag's content 1 : ta iout pin's input signal (note 4) 0 : reload type 1 : free-run type(note 5) bit symbol bit name function rw tck1 invalid in event counter mode can be 0 or 1 tmod1 a a a a a a a a a a a a a a a a figure 2.10.8 timer ai mode register in event counter mode (2) event counter mode in this mode, the timer counts an external signal or an internal timer s overflow. timers a0 and a1 can count a single-phase external signal. timers a2, a3, and a4 can count a single-phase and a two- phase external signal. table 2.10.2 lists timer specifications when counting a single-phase external signal. figure 2.10.8 shows the timer ai mode register in event counter mode. table 2.10.3 lists timer specifications when counting a two-phase external signal. figure 2.10.9 shows the timer ai mode register in event counter mode. table 2.10.2 timer specifications in event counter mode (when not processing two-phase pulse signal) item specification count source external signals input to tai in pin (effective edge can be selected by software) tb2 overflow, taj overflow count operation up count or down count can be selected by external signal or software when the timer overflows or underflows, it reloads the reload register con tents before continuing counting (note) divide ratio 1/ (ffff 16 - n + 1) for up count 1/ (n + 1) for down count n : set value count start condition count start flag is set (= 1) count stop condition count start flag is reset (= 0) interrupt request generation timing the timer overflows or underflows tai in pin function programmable i/o port or count source input tai out pin function programmable i/o port, pulse output, or up/down count select input read from timer count value can be read out by reading timer ai register write to timer when counting stopped when a value is written to timer ai register, it is written to both reload register and counter when counting in progress when a value is written to timer ai register, it is written to only reload register (transferred to counter at next reload time) select function free-run count function even when the timer overflows or underflows, the reload register content is not reloaded to it pulse output function each time the timer overflows or underflows, the tai out pin s polarity is reversed note: this does not apply when the free-run function is selected.
80 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP item specification count source two-phase pulse signals input to tai in or tai out pin count operation up count or down count can be selected by two-phase pulse signal when the timer overflows or underflows, the reload register content is reloaded and the timer starts over again (note1) divide ratio 1/ (ffff 16 - n + 1) for up count 1/ (n + 1) for down count n : set value count start condition count start flag is set (= 1) count stop condition count start flag is reset (= 0) interrupt request generation timing timer overflows or underflows tai in pin function two-phase pulse input tai out pin function two-phase pulse input read from timer count value can be read out by reading timer a2, a3, or a4 register write to timer when counting stopped when a value is written to timer a2, a3, or a4 register, it is written to both reload register and counter when counting in progress when a value is written to timer a2, a3, or a4 register, it is written to only reload register. (transferred to counter at next reload time.) select function(note 2) normal processing operation (timer a2 and timer a3) the timer counts up rising edges or counts down falling edges on the tai in pin when input signal on the tai out pin is h multiply-by-4 processing operation (timer a3 and timer a4) if the phase relationship is such that the tai in pin goes h when the input signal on the tai out pin is h , the timer counts up rising and falling edges on the tai out and tai in pins. if the phase relationship is such that the tai in pin goes l when the input signal on the tai out pin is h , the timer counts down rising and falling edges on the tai out and tai in pins. tai out tai in (i=3,4) count up all edges count up all edges count down all edges count down all edges table 2.10.3 timer specifications in event counter mode (when processing two-phase pulse signal with timers a2, a3, and a4) tai out up count up count up count down count down count down count tai in (i=2,3) note 1: this does not apply when the free-run function is selected. note 2: timer a3 alone can be selected.timer a2 is fixed to normal processing operation,and timer a4 is fixed to multiply-by-4 processing operation.
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 81 rev. 1.0 M306H2MC-XXXFP timer ai mode register (when not using two-phase pulse signal processing) symbol address when reset taimr(i = 2 to 4) 0398 16 to 039a 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 01 0 note 1: this bit is valid for timer a3 mode register. timer a2 is fixed to normal processing operation, and timer a4 is fixed to multiply-by-4 processing operation. note 2: when performing two-phase pulse signal processing, make sure the two-phase pulse signal processing operation select bit (address 0384 16 ) is set to 1 . also, always be sure to set the event/trigger select bit (address 0383 16 ) to 00 . note 3: in the case of using event counter mode as free-run type , the timer register contents may be unkown when counting begins.(refer 3. usage precaution .) timer ai mode register (when using two-phase pulse signal processing) symbol address when reset taimr(i = 2 to 4) 0398 16 to 039a 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 0 1 : event counter mode b1 b0 tmod1 tmod0 mr0 0 (must always be 0 when using two-phase pulse signal processing) 0 (must always be 0 when using two-phase pulse signal processing) mr2 mr1 mr3 0 (must always be 0 when using two-phase pulse signal processing) tck1 tck0 01 0 1 (must always be 1 when using two-phase pulse signal processing) bit symbol bit name function w r count operation type select bit two-phase pulse processing operation select bit (note 1)(note 2) 0 : reload type 1 : free-run type(note 3) 0 : normal processing operation 1 : multiply-by-4 processing operation 0 0 1 note 1: in event counter mode, the count source is selected by the event / trigger select bit (addresses 0382 16 and 0383 16 ). note 2: the settings of the corresponding port register and port direction register are invalid. note 3: valid only when counting an external signal. note 4: when an l signal is input to the tai out pin, the downcount is activated. when h , the upcount is activated. set the corresponding port direction register to 0 . note 5: in the case of using event counter mode as free-run type , the timer register contents may be unkown when counting begins.(refer 3. usage precaution.) w r operation mode select bit 0 1 : event counter mode (note 1) b1 b0 tmod0 mr0 pulse output function select bit 0 : pulse is not output (ta iout pin is a normal port pin) 1 : pulse is output (note 2) (ta iout pin is a pulse output pin) count polarity select bit (note 3) mr2 mr1 mr3 0 (must always be fixed to 0 in event counter mode) tck0 count operation type select bit 0 : counts external signal's falling edge 1 : counts external signal's rising edge up/down switching cause select bit 0 : up/down flag's content 1 : ta iout pin's input signal (note 4) 0 : reload type 1 : free-run type(note 5) bit symbol bit name function rw tck1 invalid in event counter mode can be 0 or 1 tmod1 figure 2.10.9 timer ai mode register in event counter mode
82 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP bit name timer ai mode register symbol address when reset taimr(i = 0 to 4) 0396 16 to 039a 16 00 16 function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 1 0 : one-shot timer mode b1 b0 tmod1 tmod0 mr0 pulse output function select bit 0 : pulse is not output (ta iout pin is a normal port pin) 1 : pulse is output (note 1) (tai out pin is a pulse output pin) mr2 mr1 mr3 0 (must always be 0 in one-shot timer mode) 0 0 : f 1 0 1 : f 8 1 0 : f 32 1 1 : f c32 b7 b6 tck1 tck0 count source select bit 10 0 0 : one-shot start flag is valid 1 : selected by event/trigger select register trigger select bit external trigger select bit (note 2) 0 : falling edge of tai in pin's input signal (note 3) 1 : rising edge of tai in pin's input signal (note 3) note 1: the settings of the corresponding port register and port direction register are invalid. note 2: valid only when the ta iin pin is selected by the event/trigger select bit (addresses 0382 16 and 0383 16 ). if timer overflow is selected, this bit can be 1 or 0 . note 3: set the corresponding port direction register to 0 . w r a a a a a a a a a a a a a a a a a a a a a a (3) one-shot timer mode in this mode, the timer operates only once. (see table 2.10.4) when a trigger occurs, the timer starts up and continues operating for a given period. figure 2.10.10 shows the timer ai mode register in one-shot timer mode. table 2.10.4 timer specifications in one-shot timer mode figure 2.10.10 timer ai mode register in one-shot timer mode item specification count source f 1 , f 8 , f 32 , f c32 count operation the timer counts down when the count reaches 0000 16 , the timer stops counting after reloading a new count if a trigger occurs when counting, the timer reloads a new count and restarts counting divide ratio 1/n n : set value count start condition an external trigger is input the timer overflows the one-shot start flag is set (= 1) count stop condition a new count is reloaded after the count has reached 0000 16 the count start flag is reset (= 0) interrupt request generation timing the count reaches 0000 16 tai in pin function programmable i/o port or trigger input tai out pin function programmable i/o port or pulse output read from timer when timer ai register is read, it indicates an indeterminate value write to timer when counting stopped when a value is written to timer ai register, it is written to both reload register and counter when counting in progress when a value is written to timer ai register, it is written to only reload register (transferred to counter at next reload time)
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 83 rev. 1.0 M306H2MC-XXXFP bit name timer ai mode register symbol address when reset taimr(i=0 to 4) 0396 16 to 039a 16 00 16 function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 1 1 : pwm mode b1 b0 tmod1 tmod0 mr0 mr2 mr1 mr3 0 0 : f 1 0 1 : f 8 1 0 : f 32 1 1 : f c32 b7 b6 tck1 tck0 count source select bit w r 11 1 1 (must always be 1 in pwm mode) 16/8-bit pwm mode select bit 0: functions as a 16-bit pulse width modulator 1: functions as an 8-bit pulse width modulator trigger select bit external trigger select bit (note 1) 0: falling edge of tai in pin's input signal (note 2) 1: rising edge of tai in pin's input signal (note 2) 0: count start flag is valid 1: selected by event/trigger select register note 1: valid only when the ta iin pin is selected by the event/trigger select bit (addresses 0382 16 and 0383 16 ). if timer overflow is selected, this bit can be 1 or 0 . note 2: set the corresponding port direction register to 0 . aa a aa a aa a aa a aa aa a a aa a aa a aa a figure 2.10.11 timer ai mode register in pulse width modulation mode (4) pulse width modulation (pwm) mode in this mode, the timer outputs pulses of a given width in succession. (see table 2.10.5) in this mode, the counter functions as either a 16-bit pulse width modulator or an 8-bit pulse width modulator. figure 2.10.11 shows the timer ai mode register in pulse width modulation mode. figure 2.10.12 shows the example of how a 16-bit pulse width modulator operates. figure 2.10.13 shows the ex- ample of how an 8-bit pulse width modulator operates. table 2.10.5 timer specifications in pulse width modulation mode item specification count source f 1 , f 8 , f 32 , f c32 count operation t he timer counts down (operating as an 8-bit or a 16-bit pulse width modulator) the timer reloads a new count at a rising edge of pwm pulse and continues counting the timer is not affected by a trigger that occurs when counting 16-bit pwm high level width n / fi n : set value cycle time (2 16 -1) / fi fixed 8-bit pwm high level width n (m+1) / fi n : v alues set to timer ai register s high-order address cycle time (2 8 - 1) (m+1) / fi m : values set to timer ai register s low-order address count start condition external trigger is input the timer overflows the count start flag is set (= 1) count stop condition the count start flag is reset (= 0) interrupt request generation timing pwm pulse goes l tai in pin function programmable i/o port or trigger input tai out pin function pulse output read from timer when timer ai register is read, it indicates an indeterminate value write to timer when counting stopped when a value is written to timer ai register, it is written to both reload register and counter when counting in progress when a value is written to timer ai register, it is written to only reload register (transferred to counter at next reload time)
84 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP 1 / f i x (2 1) 16 count source ta iin pin input signal pwm pulse output from ta iout pin condition : reload register = 0003 16 , when external trigger (rising edge of ta iin pin input signal) is selected trigger is not generated by this signal h h l l timer ai interrupt request bit 1 0 cleared to 0 when interrupt request is accepted, or cleared by software f i : frequency of count source (f 1 , f 8 , f 32 , f c32 ) note: n = 0000 16 to fffe 16 . 1 / f i x n count source (note1) ta iin pin input signal underflow signal of 8-bit prescaler (note2) pwm pulse output from ta iout pin h h h l l l 1 0 timer ai interrupt request bit cleared to 0 when interrupt request is accepted, or cleaerd by software f i : frequency of count source (f 1 , f 8 , f 32 , f c32 ) note 1: the 8-bit prescaler counts the count source. note 2: the 8-bit pulse width modulator counts the 8-bit prescaler's underflow signal. note 3: m = 00 16 to ff 16 ; n = 00 16 to fe 16 . condition : reload register high-order 8 bits = 02 16 reload register low-order 8 bits = 02 16 external trigger (falling edge of ta iin pin input signal) is selected 1 / f i x (m + 1) x (2 1) 8 1 / f i x (m + 1) x n 1 / f i x (m + 1) figure 2.10.13 example of how an 8-bit pulse width modulator operates figure 2.10.12 example of how a 16-bit pulse width modulator operates
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 85 rev. 1.0 M306H2MC-XXXFP timer bi mode register symbol address when reset tbimr(i = 0 to 5) 039b 16 to 039d 16 00xx0000 2 035b 16 to 035d 16 00xx0000 2 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 0 0 : timer mode 0 1 : event counter mode 1 0 : pulse period/pulse width measurement mode 1 1 : inhibited b1 b0 tck1 mr3 mr2 mr1 tmod1 mr0 tmod0 tck0 function varies with each operation mode count source select bit (function varies with each operation mode) operation mode select bit (note 1) (note 2) note 1: timer b0, timer b3. note 2: timer b1, timer b2, timer b4, timer b5. a aa a aa a aa a aa a a aa aa a aa a a aa aa a clock source selection (address 0380 16 ) event counter timer pulse period/pulse width measurement reload register (16) low-order 8 bits high-order 8 bits data bus low-order bits data bus high-order bits f 1 f 8 f 32 tbj overflow (j = i e 1. note, however, j = 2 when i = 0, j = 5 when i = 3) can be selected in only event counter mode count start flag f c32 polarity switching and edge pulse tbi in (i = 0 to 5) counter reset circuit counter (16) tbi address tbj timer b0 0391 16 0390 16 timer b2 timer b1 0393 16 0392 16 timer b0 timer b2 0395 16 0394 16 timer b1 timer b3 0351 16 0350 16 timer b5 timer b4 0353 16 0352 16 timer b3 timer b5 0355 16 0354 16 timer b4 2.10.2 timer b figure 2.10.14 shows the block diagram of timer b. figures 2.10.15 and 2.10.16 show the timer b- related registers. use the timer bi mode register (i = 0 to 5) bits 0 and 1 to choose the desired mode. timer b has three operation modes listed as follows: ?timer mode: the timer counts an internal count source. ?event counter mode: the timer counts pulses from an external source or a timer overflow. ?pulse period/pulse width measuring mode: the timer measures an external signal's pulse period or pulse width. figure 2.10.15 timer b-related registers (1) figure 2.10.14 block diagram of timer b
86 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP symbol address when reset tabsr 0380 16 00 16 count start flag bit name bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa timer b2 count start flag timer b1 count start flag timer b0 count start flag timer a4 count start flag timer a3 count start flag timer a2 count start flag timer a1 count start flag timer a0 count start flag 0 : stops counting 1 : starts counting tb2s tb1s tb0s ta4s ta3s ta2s ta1s ta0s function a a a a a a a a a a a a a a a a a a a a a a symbol address when reset cpsrf 0381 16 0xxxxxxx 2 clock prescaler reset flag bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 aaaaaaaaaaaaaaaa a aaaaaaaaaaaaaa a aaaaaaaaaaaaaaaa clock prescaler reset flag 0 : no effect 1 : prescaler is reset (when read, the value is 0 ) cpsr a a symbol address when reset tb0 0391 16 , 0390 16 indeterminate tb1 0393 16 , 0392 16 indeterminate tb2 0395 16 , 0394 16 indeterminate tb3 0351 16 , 0350 16 indeterminate tb4 0353 16 , 0352 16 indeterminate tb5 0355 16 , 0354 16 indeterminate b7 b0 b7 b0 (b15) (b8) timer bi register (note) w r pulse period / pulse width measurement mode measures a pulse period or width timer mode 0000 16 to ffff 16 counts the timer's period function values that can be set event counter mode 0000 16 to ffff 16 counts external pulses input or a timer overflow note: read and write data in 16-bit units. a a a a a symbol address when reset tbsr 0340 16 000xxxxx 2 timer b3, 4, 5 count start flag bit name bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa a aaaaaaaaaaaaaa a aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa timer b5 count start flag timer b4 count start flag timer b3 count start flag 0 : stops counting 1 : starts counting tb5s tb4s tb3s nothing is assigned. in an attempt to write to these bits, write 0 . the value, if read, turns out to be 0 . function a a a a a a a a nothing is assigned. in an attempt to write to these bits, write 0 . the value, if read, turns out to be 0 . figure 2.10.16 timer b-related registers (2)
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 87 rev. 1.0 M306H2MC-XXXFP note 1: timer b0, timer b3. note 2: timer b1, timer b2, timer b4, timer b5. timer bi mode register symbol address when reset tbimr(i=0 to 5) 039b 16 to 039d 16 00xx0000 2 035b 16 to 035d 16 00xx0000 2 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 aa aa a a operation mode select bit 0 0 : timer mode b1 b0 tmod1 tmod0 mr0 invalid in timer mode can be 0 or 1 mr2 mr1 mr3 0 0 : f 1 0 1 : f 8 1 0 : f 32 1 1 : f c32 tck1 tck0 count source select bit 0 invalid in timer mode. in an attempt to write to this bit, write 0 . the value, if read in timer mode, turns out to be indeterminate. 0 0 (fixed to 0 in timer mode ; i = 0, 3) nothing is assiigned (i = 1, 2, 4, 5). in an attempt to write to this bit, write 0 . the value, if read, turns out to be indeterminate. (note 1) (note 2) b7 b6 a a a a a a a a a a a a a a a a a a figure 2.10.17 timer bi mode register in timer mode (1) timer mode in this mode, the timer counts an internally generated count source. (see table 2.10.6) figure 2.10.17 shows the timer bi mode register in timer mode. table 2.10.6 timer specifications in timer mode item specification count source f 1 , f 8 , f 32 , f c32 count operation counts down when the timer underflows, it reloads the reload register contents before continuing counting divide ratio 1/(n+1) n : set value count start condition count start flag is set (= 1) count stop condition count start flag is reset (= 0) interrupt request generation timing the timer underflows tbi in pin function programmable i/o port read from timer count value is read out by reading timer bi register write to timer when counting stopped when a value is written to timer bi register, it is written to both reload register and counter when counting in progress when a value is written to timer bi register, it is written to only reload register (transferred to counter at next reload time)
88 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP timer bi mode register symbol address when reset tbimr(i=0 to 5) 039b 16 to 039d 16 00xx0000 2 035b 16 to 035d 16 00xx0000 2 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 aa aa operation mode select bit 0 1 : event counter mode b1 b0 tmod1 tmod0 mr0 count polarity select bit (note 1) mr2 mr1 mr3 invalid in event counter mode. in an attempt to write to this bit, write 0 . the value, if read in event counter mode, turns out to be indeterminate. tck1 tck0 01 0 0 : counts external signal's falling edges 0 1 : counts external signal's rising edges 1 0 : counts external signal's falling and rising edges 1 1 : inhibited b3 b2 nothing is assigned (i = 1, 2, 4, 5). in an attempt to write to this bit, write 0 . the value, if read, turns out to be indeterminate. note 1: valid only when input from the tbi in pin is selected as the event clock. if timer's overflow is selected, this bit can be 0 or 1 . note 2: timer b0, timer b3. note 3: timer b1, timer b2, timer b4, timer b5. note 4: set the corresponding port direction register to 0 . invalid in event counter mode. can be 0 or 1 . event clock select 0 : input from tbi in pin (note 4) 1 : tbj overflow (j = i 1; however, j = 2 when i = 0, j = 5 when i = 3) 0 (fixed to 0 in event counter mode; i = 0, 3) (note 2) (note 3) aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa figure 2.10.18 timer bi mode register in event counter mode (2) event counter mode in this mode, the timer counts an external signal or an internal timer's overflow. (see table 2.10.7) figure 2.10.18 shows the timer bi mode register in event counter mode. table 2.10.7 timer specifications in event counter mode item specification count source external signals input to tbi in pin effective edge of count source can be a rising edge, a falling edge, or falling and rising edges as selected by software count operation counts down when the timer underflows, it reloads the reload register contents before continuing counting divide ratio 1/(n+1) n : set value count start condition count start flag is set (= 1) count stop condition count start flag is reset (= 0) interrupt request generation timing the timer underflows tbi in pin function count source input read from timer count value can be read out by reading timer bi register write to timer when counting stopped when a value is written to timer bi register, it is written to both reload register and counter when counting in progress when a value is written to timer bi register, it is written to only reload register (transferred to counter at next reload time)
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 89 rev. 1.0 M306H2MC-XXXFP (3) pulse period/pulse width measurement mode in this mode, the timer measures the pulse period or pulse width of an external signal. (see table 2.10.8) figure 2.10.19 shows the timer bi mode register in pulse period/pulse width measurement mode. figure 2.10.20 shows the operation timing when measuring a pulse period. figure 2.10.21 shows the operation timing when measuring a pulse width. figure 2.10.19 timer bi mode register in pulse period/pulse width measurement mode table 2.10.8 timer specifications in pulse period/pulse width measurement mode note 1: an interrupt request is not generated when the first effective edge is input after the timer has started counting. note 2: the value read out from the timer bi register is indeterminate until the second effective edge is input after the timer. item specification count source f 1 , f 8 , f 32 , f c32 count operation up count counter value 0000 16 is transferred to reload register at measurement pulse's effective edge and the timer continues counting count start condition count start flag is set (= 1) count stop condition count start flag is reset (= 0) interrupt request generation timing when measurement pulse's effective edge is input (note 1) when an overflow occurs. (simultaneously, the timer bi overflow flag changes to 1 . the timer bi overflow flag changes to 0 when the count start flag is 1 and a value is written to the timer bi mode register.) tbi in pin function measurement pulse input read from timer when timer bi register is read, it indicates the reload register s content (measurement result) (note 2) write to timer cannot be written to timer bi mode register symbol address when reset tbimr(i=0 to 5) 039b 16 to 039d 16 00xx0000 2 035b 16 to 035d 16 00xx0000 2 bit name bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 1 0 : pulse period / pulse width measurement mode b1 b0 tmod1 tmod0 mr0 measurement mode select bit mr2 mr1 mr3 tck1 tck0 0 1 0 0 : pulse period measurement (interval between measurement pulse's falling edge to falling edge) 0 1 : pulse period measurement (interval between measurement pulse's rising edge to rising edge) 1 0 : pulse width measurement (interval between measurement pulse's falling edge to rising edge, and between rising edge to falling edge) 1 1 : inhibited function b3 b2 nothing is assigned (i = 1, 2, 4, 5). in an attempt to write to this bit, write 0 . the value, if read, turns out to be indeterminate. count source select bit timer bi overflow flag ( note 1) 0 : timer did not overflow 1 : timer has overflowed 0 0 : f 1 0 1 : f 8 1 0 : f 32 1 1 : f c32 b7 b6 note 1: it is indeterminate when reset. the timer bi overflow flag changes to 0 when the count start flag is 1 and a value is written to the timer bi mode register. this flag cannot be set to 1 by software. note 2: timer b0, timer b3. note 3: timer b1, timer b2, timer b4, timer b5. 0 (fixed to 0 in pulse period/pulse width measurement mode; i = 0, 3) (note 2) (note 3)
90 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP figure 2.10.21 operation timing when measuring a pulse width measurement pulse h count source count start flag timer bi interrupt request bit timing at which counter reaches 0000 16 1 1 transfer (measured value) transfer (measured value) l 0 0 timer bi overflow flag 1 0 note 1: counter is initialized at completion of measurement. note 2: timer has overflowed. (note 1) (note 1) (note 1) transfer (measured value) (note 1) cleared to 0 when interrupt request is accepted, or cleared by software. (note 2) transfer (indeterminate value) reload register counter transfer timing figure 2.10.20 operation timing when measuring a pulse period count source measurement pulse count start flag timer bi interrupt request bit timing at which counter reaches 0000 16 h 1 transfer (indeterminate value) l 0 0 timer bi overflow flag 1 0 note 1: counter is initialized at completion of measurement. note 2: timer has overflowed. (note 1) (note 1) when measuring measurement pulse time interval from falling edge to falling edge (note 2) cleared to 0 when interrupt request is accepted, or cleared by software. transfer (measured value) 1 reload register counter transfer timing
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 91 rev. 1.0 M306H2MC-XXXFP note 1: only when clock synchronous serial i/o mode. note 2: only when clock synchronous serial i/o mode and 8-bit uart mode. note 3: only when uart mode. note 4: using for sim interface. uart0 uart1 uart2 function clk polarity selection continuous receive mode selection lsb first / msb first selection impossible transfer clock output from multiple pins selection impossible possible (note 1) possible (note 1) possible (note 1) possible (note 1) possible (note 1) possible (note 1) possible (note 1) possible (note 1) possible (note 2) possible (note 1) impossible serial data logic switch impossible sleep mode selection impossible impossible txd, rxd i/o polarity switch impossible possible cmos output txd, rxd port output format cmos output n-channel open-drain output impossible parity error signal output impossible impossible bus collision detection impossible possible possible (note 3) possible (note 3) possible (note 4) possible (note 4) 2.11 serial i/o serial i/o is configured as five channels: uart0, uart1, uart2, s i/o3 and s i/o4. 2.11.1 uart0 to 2 uart0, uart1 and uart2 each have an exclusive timer to generate a transfer clock, so they oper- ate independently of each other. figure 2.11.1 shows the block diagram of uart0, uart1 and uart2. figures 2.11.2 and 2.11.3 show the block diagram of the transmit/receive unit. uarti (i = 0 to 2) has two operation modes: a clock synchronous serial i/o mode and a clock asyn- chronous serial i/o mode (uart mode). the contents of the serial i/o mode select bits (bits 0 to 2 at addresses 03a0 16 , 03a8 16 and 0378 16 ) determine whether uarti is used as a clock synchronous serial i/o or as a uart. although a few functions are different, uart0, uart1 and uart2 have almost the same functions. uart0 through uart2 are almost equal in their functions with minor exceptions. uart2, in particu- lar, is compliant with the sim interface with some extra settings added in clock-asynchronous serial i/o mode (note). it also has the bus collision detection function that generates an interrupt request if the txd pin and the rxd pin are different in level. table 2.11.1 shows the comparison of functions of uart0 through uart2, and figures 2.11.4 to 2.11.8 show the registers related to uarti. note: sim : subscriber identity module table 2.11.1 comparison of functions of uart0 through uart2
92 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP figure 2.11.1 block diagram of uarti (i = 0 to 2) clk 0 n0 : values set to uart0 bit rate generator (brg0) n1 : values set to uart1 bit rate generator (brg1) n2 : values set to uart2 bit rate generator (brg2) rxd 2 reception control circuit transmission control circuit 1 / (n 2 +1) 1/16 1/16 1/2 bit rate generator (address 0379 16 ) clock synchronous type (when internal clock is selected) uart reception clock synchronous type uart transmission clock synchronous type clock synchronous type (when internal clock is selected) clock synchronous type (when external clock is selected) receive clock transmit clock clk 2 cts 2 / rts 2 f 1 f 8 f 32 vcc rts 2 cts 2 txd 2 (uart2) rxd polarity reversing circuit txd polarity reversing circuit rxd 0 1 / (n 0 +1) 1/2 bit rate generator (address 03a1 16 ) clock synchronous type (when internal clock is selected) uart reception clock synchronous type uart transmission clock synchronous type clock synchronous type (when internal clock is selected) clock synchronous type (when external clock is selected) receive clock transmit clock clock source selection cts 0 / rts 0 f 1 f 8 f 32 reception control circuit transmission control circuit internal external vcc rts 0 cts 0 txd 0 transmit/ receive unit rxd 1 1 / (n 1 +1) 1/16 1/16 1/2 bit rate generator (address 03a9 16 ) clock synchronous type (when internal clock is selected) uart reception clock synchronous type uart transmission clock synchronous type clock synchronous type (when internal clock is selected) clock synchronous type (when external clock is selected) receive clock transmit clock clk 1 clock source selection f 1 f 8 f 32 reception control circuit transmission control circuit internal external rts 1 cts 1 txd 1 (uart1) (uart0) clk polarity reversing circuit clk polarity reversing circuit cts/rts disabled clock output pin select switch cts/rts disabled cts/rts selected cts/rts disabled v cc cts/rts disabled cts/rts disabled cts/rts disabled cts/rts selected clk polarity reversing circuit internal external clock source selection transmit/ receive unit transmit/ receive unit 1/16 1/16 cts 1 / rts 1 / clks 1 cts/rts selected
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 93 rev. 1.0 M306H2MC-XXXFP sp sp par 2sp 1sp uart uart (7 bits) uart (8 bits) uart (7 bits) uart (9 bits) clock synchronous type clock synchronous type txdi uarti transmit register par enabled par disabled d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 sp: stop bit par: parity bit uarti transmit buffer register msb/lsb conversion circuit uart (8 bits) uart (9 bits) clock synchronous type uarti receive buffer register uarti receive register 2sp 1sp par enabled par disabled uart uart (7 bits) uart (9 bits) clock synchronous type clock synchronous type uart (7 bits) uart (8 bits) rxdi clock synchronous type uart (8 bits) uart (9 bits) address 03a6 16 address 03a7 16 address 03ae 16 address 03af 16 address 03a2 16 address 03a3 16 address 03aa 16 address 03ab 16 data bus low-order bits msb/lsb conversion circuit d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 8 0000000 sp sp par ? data bus high-order bits figure 2.11.2 block diagram of uarti (i = 0, 1) transmit/receive unit
94 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP sp sp par 2sp 1sp uart uart (7 bits) uart (8 bits) uart(7 bits) uart (9 bits) clock synchronous type clock synchronous type data bus low-order bits txd2 uart2 transmit register par disabled par enabled d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 uart2 transmit buffer register uart (8 bits) uart (9 bits) clock synchronous type uart2 receive buffer register uart2 receive register 2sp 1sp uart (7 bits) uart (8 bits) uart(7 bits) uart (9 bits) clock synchronous type clock synchronous type rxd2 uart (8 bits) uart (9 bits) address 037e 16 address 037f 16 address 037a 16 address 037b 16 data bus high-order bits d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 8 0000000 sp sp par 0 reverse no reverse error signal output circuit rxd data reverse circuit error signal output enable error signal output disable reverse no reverse logic reverse circuit + msb/lsb conversion circuit logic reverse circuit + msb/lsb conversion circuit par enabled par disabled uart clock synchronous type txd data reverse circuit sp: stop bit par: parity bit figure 2.11.3 block diagram of uart2 transmit/receive unit
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 95 rev. 1.0 M306H2MC-XXXFP figure 2.11.4 uarti i/o-related registers (1) b7 uarti bit rate generator b0 symbol address when reset u0brg 03a1 16 indeterminate u1brg 03a9 16 indeterminate u2brg 0379 16 indeterminate function assuming that set value = n, brgi divides the count source by n + 1 00 16 to ff 16 values that can be set w r b7 b0 (b15) (b8) b7 b0 uarti transmit buffer register function transmit data nothing is assigned. in an attempt to write to these bits, write 0 . the value, if read, turn out to be indeterminate. symbol address when reset u0tb 03a3 16 , 03a2 16 indeterminate u1tb 03ab 16 , 03aa 16 indeterminate u2tb 037b 16 , 037a 16 indeterminate w r (b15) symbol address when reset u0rb 03a7 16 , 03a6 16 indeterminate u1rb 03af 16 , 03ae 16 indeterminate u2rb 037f 16 , 037e 16 indeterminate b7 b0 (b8) b7 b0 uarti receive buffer register function (during uart mode) function (during clock synchronous serial i/o mode) bit name bit symbol 0 : no framing error 1 : framing error found 0 : no parity error 1 : parity error found 0 : no error 1 : error found note 1: bits 15 through 12 are set to 0 when the serial i/o mode select bit (bits 2 to 0 at addresses 03a0 16 , 03a8 16 and 0378 16 ) are set to 000 2 or the receive enable bit is set to 0 . (bit 15 is set to 0 when bits 14 to 12 all are set to 0 .) bits 14 and 13 are also set to 0 when the lower byte of the uarti receive buffer register (addresses 03a6 16 , 03ae 16 and 037e 16 ) is read out. note 2: arbitration lost detecting flag is allocated to u2rb and noting but 0 may be written. nothing is note 1: write a value to the register while transmit/receive stop. note 2: use mov instruction to write to this register. assigned in bit 11 of u0rb and u1rb. these bits can neither be set or reset. when read, the value of this bit is 0 . invalid invalid invalid oer fer per sum overrun error flag (note 1) framing error flag (note 1) parity error flag (note 1) error sum flag (note 1) 0 : no overrun error 1 : overrun error found 0 : no overrun error 1 : overrun error found nothing is assigned. in an attempt to write to these bits, write 0 . the value, if read, turns out to be 0 . receive data w r receive data abt arbitration lost detecting flag (note 2) invalid 0 : not detected 1 : detected note: use mov instruction to write this register.
96 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP uarti transmit/receive mode register symbol address when reset uimr(i=0,1) 03a0 16 , 03a8 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol w r must be fixed to 001 0 0 0 : serial i/o invalid 0 1 0 : must not be set 0 1 1 : must not be set 1 1 1 : must not be set b2 b1 b0 ckdir smd1 smd0 serial i/o mode select bit smd2 internal/external clock select bit stps pry prye slep parity enable bit 0 : internal clock 1 : external clock (note) stop bit length select bit odd/even parity select bit sleep select bit 0 : one stop bit 1 : two stop bits 0 : parity disabled 1 : parity enabled 0 : sleep mode deselected 1 : sleep mode selected 1 0 0 : transfer data 7 bits length 1 0 1 : transfer data 8 bits length 1 1 0 : transfer data 9 bits length 0 0 0 : serial i/o invalid 0 1 0 : must not be set 0 1 1 : must not be set 1 1 1 : must not be set b2 b1 b0 0 : internal clock 1 : external clock (note) invalid valid when bit 6 = 1 0 : odd parity 1 : even parity invalid invalid must always be 0 function (during uart mode) function (during clock synchronous serial i/o mode) uart2 transmit/receive mode register symbol address when reset u2mr 0378 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol w r must be fixed to 001 0 0 0 : serial i/o invalid 0 1 0 : (note1) 0 1 1 : must not be set 1 1 1 : must not be set b2 b1 b0 ckdir smd1 smd0 serial i/o mode select bit smd2 internal/external clock select bit stps pry prye iopol parity enable bit 0 : internal clock 1 : external clock (note2) stop bit length select bit odd/even parity select bit txd, rxd i/o polarity reverse bit 0 : one stop bit 1 : two stop bits 0 : parity disabled 1 : parity enabled 0 : no reverse 1 : reverse usually set to 0 1 0 0 : transfer data 7 bits length 1 0 1 : transfer data 8 bits length 1 1 0 : transfer data 9 bits length 0 0 0 : serial i/o invalid 0 1 0 : must not be set 0 1 1 : must not be set 1 1 1 : must not be set b2 b1 b0 invalid valid when bit 6 = 1 0 : odd parity 1 : even parity invalid invalid 0 : no reverse 1 : reverse usually set to 0 function (during uart mode) function (during clock synchronous serial i/o mode) notes1: bit 2 to bit 0 are set to 010 2 when i 2 c mode is used. 2: set the corresponding direction register to 0 . note: set the corresponding direction register to "0". must always be fixed to 0 figure 2.11.5 uartil i/o-related registers (2)
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 97 rev. 1.0 M306H2MC-XXXFP uarti transmit/receive control register 0 symbol address when reset uic0(i=0,1) 03a4 16 , 03ac 16 08 16 b7 b6 b5 b4 b3 b2 b1 b0 function (during uart mode) w r function (during clock synchronous serial i/o mode) txept clk1 clk0 crs crd nch ckpol brg count source select bit transmit register empty flag 0 : transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 : transmit data is output at rising edge of transfer clock and receive data is input at falling edge clk polarity select bit cts/rts function select bit cts/rts disable bit data output select bit 0 0 : f 1 is selected 0 1 : f 8 is selected 1 0 : f 32 is selected 1 1 : must not be set b1 b0 0 : lsb first 1 : msb first 0 : data present in transmit register (during transmission) 1 : no data present in transmit register (transmission completed) 0 : cts/rts function enabled 1 : cts/rts function disabled (p6 0 and p6 4 function as programmable i/o port) 0 : txdi pin is cmos output 1 : txdi pin is n-channel open-drain output uform transfer format select bit 0 0 : f 1 is selected 0 1 : f 8 is selected 1 0 : f 32 is selected 1 1 : must not be set b1 b0 valid when bit 4 = 0 0 : cts function is selected (note 1) 1 : rts function is selected (note 2) valid when bit 4 = 0 0 : cts function is selected (note 1) 1 : rts function is selected (note 2) 0 : data present in transmit register (during transmission) 1 : no data present in transmit register (transmission completed) 0: txdi pin is cmos output 1: txdi pin is n-channel open-drain output must always be 0 bit name bit symbol must always be 0 note 1: set the corresponding port direction register to 0 . note 2: the settings of the corresponding port register and port direction register are invalid. 0 : cts/rts function enabled 1 : cts/rts function disabled (p6 0 and p6 4 function as programmable i/o port) uart2 transmit/receive control register 0 symbol address when reset u2c0 037c 16 08 16 b7 b6 b5 b4 b3 b2 b1 b0 function (during uart mode) w r function (during clock synchronous serial i/o mode) txept clk1 clk0 crs crd ckpol brg count source select bit transmit register empty flag 0 : transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 : transmit data is output at rising edge of transfer clock and receive data is input at falling edge clk polarity select bit cts/rts function select bit cts/rts disable bit 0 0 : f 1 is selected 0 1 : f 8 is selected 1 0 : f 32 is selected 1 1 : must not be set b1 b0 0 : lsb first 1 : msb first 0 : data present in transmit register (during transmission) 1 : no data present in transmit register (transmission completed) 0 : cts/rts function enabled 1 : cts/rts function disabled (p7 3 functions programmable i/o port) 0 : txdi pin is cmos output 1 : txdi pin is n-channel open-drain output uform transfer format select bit (note 3) 0 0 : f 1 is selected 0 1 : f 8 is selected 1 0 : f 32 is selected 1 1 : must not be set b1 b0 valid when bit 4 = 0 0 : cts function is selected (note 1) 1 : rts function is selected (note 2) valid when bit 4 = 0 0 : cts function is selected (note 1) 1 : rts function is selected (note 2) 0 : data present in transmit register (during transmission) 1 : no data present in transmit register (transmission completed) 0: txdi pin is cmos output 1: txdi pin is n-channel open-drain output must always be 0 bit name bit symbol note 1: set the corresponding port direction register to 0 . note 2: the settings of the corresponding port register and port direction register are invalid. note 3: only clock synchronous serial i/o mode and 8-bit uart mode are valid. 0 : cts/rts function enabled 1 : cts/rts function disabled (p7 3 functions programmable i/o port) nothing is assigned. in an attempt to write to this bit, write 0 . the value, if read, turns out to be 0 . 0 : lsb first 1 : msb first figure 2.11.6 uarti i/o-related registers (3)
98 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP figure 2.11.7 uarti i/o-related registers (4) uarti transmit/receive control register 1 symbol address when reset uic1(i=0,1) 03a5 16 , 03ad 16 02 16 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol w r function (during uart mode) function (during clock synchronous serial i/o mode) te ti re ri transmit enable bit receive enable bit receive complete flag transmit buffer empty flag 0 : transmission disabled 1 : transmission enabled 0 : data present in transmit buffer register 1 : no data present in transmit buffer register 0 : reception disabled 1 : reception enabled 0 : transmission disabled 1 : transmission enabled 0 : data present in transmit buffer register 1 : no data present in transmit buffer register 0 : reception disabled 1 : reception enabled 0 : no data present in receive buffer register 1 : data present in receive buffer register 0 : no data present in receive buffer register 1 : data present in receive buffer register nothing is assigned. in an attempt to write to these bits, write 0 . the value, if read, turns out to be 0 . uart2 transmit/receive control register 1 symbol address when reset u2c1 037d 16 02 16 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol w r function (during uart mode) function (during clock synchronous serial i/o mode) te ti re ri transmit enable bit receive enable bit receive complete flag transmit buffer empty flag 0 : transmission disabled 1 : transmission enabled 0 : data present in transmit buffer register 1 : no data present in transmit buffer register 0 : reception disabled 1 : reception enabled 0 : transmission disabled 1 : transmission enabled 0 : data present in transmit buffer register 1 : no data present in transmit buffer register 0 : reception disabled 1 : reception enabled 0 : no data present in receive buffer register 1 : data present in receive buffer register 0 : no data present in receive buffer register 1 : data present in receive buffer register u2irs uart2 transmit interrupt cause select bit 0 : transmit buffer empty (ti = 1) 1 : transmit is completed (txept = 1) 0 : transmit buffer empty (ti = 1) 1 : transmit is completed (txept = 1) u2rrm uart2 continuous receive mode enable bit 0 : continuous receive mode disabled 1 : continuous receive mode enabled invalid data logic select bit 0 : no reverse 1 : reverse 0 : no reverse 1 : reverse u2lch u2ere error signal output enable bit must be fixed to 0 0 : output disabled 1 : output enabled a a a a a a a a a a a a a a a a a a a a a a a a a a a a
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 99 rev. 1.0 M306H2MC-XXXFP note: when using multiple pins to output the transfer clock, the following requirements must be met: uart1 internal/external clock select bit (bit 3 at address 03a8 16 ) = 0. uart transmit/receive control register 2 symbol address when reset ucon 03b0 16 x0000000 2 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol w r function (during uart mode) function (during clock synchronous serial i/o mode) clkmd0 clkmd1 reserved bit uart0 transmit interrupt cause select bit uart0 continuous receive mode enable bit 0 : continuous receive mode disabled 1 : continuous receive mode enable uart1 continuous receive mode enable bit clk/clks select bit 0 uart1 transmit interrupt cause select bit 0 : transmit buffer empty (tl = 1) 1 : transmission completed (txept = 1) 0 : transmit buffer empty (tl = 1) (txept = 1) 1 : transmission completed 0 : normal mode (clk output is clk1 only) 1 : transfer clock output from multiple pins function selected 0 : continuous receive mode disabled 1 : continuous receive mode enabled nothing is assigned. in an attempt to write to this bit, write 0. the value, if read, turns out to be indeterminate. 0 : transmit buffer empty (tl = 1) 1 : transmission completed (txept = 1) 0 : transmit buffer empty (tl = 1) 1 : transmission completed (txept = 1) must always be 0 u0irs u1irs u0rrm u1rrm invalid invalid invalid clk/clks select bi t 1 (note) valid when bit 5 = 1 0 : clock output to clk1 1 : clock output to clks1 uart2 special mode register symbol address when reset u2smr 0377 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol function (during clock synchronous serial i/o mode) abscs acse sss i 2 c mode selection bit bus busy flag 0 : stop condition detected 1 : start condition detected scll sync output enable bit bus collision detect sampling clock select bit arbitration lost detecting flag control bit 0 : normal mode 1 : i 2 c mode 0 : update per bit 1 : update per byte iicm abc bbs lsyn 0 : disabled 1 : enabled transmit start condition select bit a u t o c l ear f unc ti on select bit of transmit enable bit must always be 0 must always be 0 must always be 0 0 must always be 0 sdds sda di g i ta l d e l ay selection bit (notes 2 and 3) w r function (during uart mode) 0 : ordinary 1 : falling edge of rxd2 must always be 0 0 : rising edge of transfer clock 1 : underflow signal of timer a0 0 : no auto clear function 1 : auto clear at occurrence of bus collision must always be 0 must always be 0 must always be 0 must always be 0 0 : analog delay output selection 1 : digital delay output selection (note 1) notes 1: nothing but "0" may be written. 2: do not write "1" except at i 2 c mode. must always be 0 at normal mode. bit 7 to bit5 (dl2 to dl0 = sda digital delay value setting bit) of uart2 special mode register 3 (u2smr3/address 0375 16 ) are initialized and become 000 when this bit is "0", analog delay circuit is selected. reading and writing u2smr3 are enable when sdds = "0". 3: delaying ; only analog delay value when analog delay is selected, and only digital delay value when digital delay is selected. figure 2.11.8 uarti i/o-related registers (5)
100 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP figure 2.11.9 uarti -related registers (6) uart2 special mode register 2 (i 2 c bus exclusive register) symbol address when reset u2smr2 0376 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol w r function stac swc2 sdhi i c mode selection bit 2 scl wait output bit 0 : disabled 1 : enabled sda output stop bit uart2 initialization bit clock-synchronous bit refer to table 2.11.11 0 : disabled 1 : enabled iicm2 csc swc als 0 : disabled 1 : enabled sda output disable bit scl wait output bit 2 0: enabled 1: disabled (high impedance) 0 : disabled 1 : enabled 0: uart2 clock 1: 0 output 2 shtc start/stop condition control bit set this bit to "1" in i 2 c mode (refer to table 2.11.12) uart2 special mode register 3 (i 2 c bus exclusive register) symbol address when reset u2smr3 0375 16 indeterminate b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol function (i 2 c bus exclusive) sda digital delay value setting bit (note1, note2, note3, note4) b7 b6 b5 dl0 dl1 dl2 (initializing value is "00 16 " at sdds = "1") nothing is assigned. in an attempt to write to this bit, write 0 . the value, if read, turns out to be 0 . 0 is read out when sdds = 1. (note1) w r notes 1: reading and writing is possible when bit7 (sdds = sda digital delay selection bit) of uart2 special mode register (u2smr/address 0377 16 ) is "1". when set sdds = "1" and read out initialized value of uart2 special mode register 3(u2smr3), this value is "00 16 ".when set sdds = "1" and write to uart2 special mode register 3(u2smr3), set "0" to bit 0 to bit 4. when sdds = "0", writing is enable. when read out, this value is indeterminate. 2: when sdds = "0" , this bit is initialized and become "000", selected analog delay circuit. this bit is become "000" after end reset released, and selected analog delay circuit. reading out is possible when only sdds = "1". when sdds = "0", value which was read out is indeterminate. 3: delaying ; only analog delay value when analog delay is selected, and only digital delay value when digital delay is selected. 4: delay level depends on scl pin and sda pin. and, when use external clock, delay is increase around 100ns. so test first, and use this. 0 0 0 : analog delay 0 0 1 : 1 2 cycle of 1/f (xin)(digital delay) 0 1 0 : 2 3 cycle of 1/f (xin)(digital delay) 0 1 1 : 3 4 cycle of 1/f (xin)(digital delay) 1 0 0 : 4 5 cycle of 1/f (xin)(digital delay) 1 0 1 : 5 6 cycle of 1/f (xin)(digital delay) 1 1 0 : 6 7 cycle of 1/f (xin)(digital delay) 1 1 1 : 7 8 cycle of 1/f (xin)(digital delay)
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 101 rev. 1.0 M306H2MC-XXXFP 2.11.2 clock synchronous serial i/o mode the clock synchronous serial i/o mode uses a transfer clock to transmit and receive data. tables 2.11.2 and 2.11.3 list the specifications of the clock synchronous serial i/o mode. figur 2.11.10 shows the uarti transmit/receive mode register. table 2.11.2 specifications of clock synchronous serial i/o mode (1) interrupt request generation timing item specification transfer data format transfer data length: 8 bits transfer clock when internal clock is selected (bit 3 at addresses 03a0 16 , 03a8 16 , 0378 16 = 0 ) : fi/ 2(n+1) (note 1) fi = f 1 , f 8 , f 32 when external clock is selected (bit 3 at addresses 03a0 16 , 03a8 16 , 0378 16 = 1 ) : input from clki pin transmission/reception control _______ _______ _______ _______ cts function/ rts function/ cts , rts function chosen to be invalid transmission start condition to start transmission, the following requirements must be met: _ transmit enable bit (bit 0 at addresses 03a5 16 , 03ad 16 , 037d 16 ) = 1 _ transmit buffer empty flag (bit 1 at addresses 03a5 16 , 03ad 16 , 037d 16 ) = 0 _______ _______ _ when cts function selected, cts input level = l furthermore, if external clock is selected, the following requirements must also be met: _ clki polarity select bit (bit 6 at addresses 03a4 16 , 03ac 16 , 037c 16 ) = 0 : clki input level = h _ clki polarity select bit (bit 6 at addresses 03a4 16 , 03ac 16 , 037c 16 ) = 1 : clki input level = l reception start condition to start reception, the following requirements must be met: _ receive enable bit (bit 2 at addresses 03a5 16 , 03ad 16 , 037d 16 ) = 1 _ transmit enable bit (bit 0 at addresses 03a5 16 , 03ad 16 , 037d 16 ) = 1 _ transmit buffer empty flag (bit 1 at addresses 03a5 16 , 03ad 16 , 037d 16 ) = 0 furthermore, if external clock is selected, the following requirements must also be met: _ clki polarity select bit (bit 6 at addresses 03a4 16 , 03ac 16 , 037c 16 ) = 0 : clki input level = h _ clki polarity select bit (bit 6 at addresses 03a4 16 , 03ac 16 , 037c 16 ) = 1 : clki input level = l when transmitting _ transmit interrupt cause select bit (bits 0, 1 at address 03b0 16 , bit 4 at address 037d 16 ) = 0 : interrupts requested when data transfer from uarti transfer buffer register to uarti transmit register is completed _ transmit interrupt cause select bit (bits 0, 1 at address 03b0 16 , bit 4 at address 037d 16 ) = 1 : interrupts requested when data transmission from uarti transfer register is completed when receiving _ interrupts requested when data transfer from uarti receive register to uarti receive buffer register is completed error detection overrun error (note 2) this error occurs when the next data is ready before contents of uarti receive buffer register are read out note 1: n denotes the value 00 16 to ff 16 that is set to the uart bit rate generator. note 2: if an overrun error occurs, the uarti receive buffer will have the next data written in. note also that the uarti receive interrupt request bit does not change.
102 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP table 2.11.3 specifications of clock synchronous serial i/o mode (2) item specification select function clk polarity selection whether transmit data is output/input at the rising edge or falling edge of the transfer clock can be selected lsb first/msb first selection whether transmission/reception begins with bit 0 or bit 7 can be selected continuous receive mode selection reception is enabled simultaneously by a read from the receive buffer register transfer clock output from multiple pins selection (uart1) uart1 transfer clock can be chosen by software to be output from one of the two pins set switching serial data logic (uart2) whether to reverse data in writing to the transmission buffer register or reading the reception buffer register can be selected. txd, rxdi/opolarity reverse (uart2) this function is reversing txd port output and rxd port input. all i/o data level is reversed.
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 103 rev. 1.0 M306H2MC-XXXFP figure 2.11.10 uarti transmit/receive mode register in clock synchronous serial i/o mode symbol address when reset uimr(i=0,1) 03a0 16 , 03a8 16 00 16 ckdir uarti transmit/receive mode registers internal/external clock select bit stps pry prye slep 0 : internal clock 1 : external clock (see note 1) bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 0 (must always be 0 in clock synchronous serial i/o mode) 01 0 smd0 smd1 smd2 serial i/o mode select bit 0 0 1 : clock synchronous serial i/o mode b2 b1 b0 0 invalid in clock synchronous serial i/o mode symbol address when reset u2mr 0378 16 00 16 ckdir uart2 transmit/receive mode register internal/external clock select bit stps pry prye iopol 0 : internal clock 1 : external clock (see note 2) bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 01 0 smd0 smd1 smd2 serial i/o mode select bit 0 0 1 : clock synchronous serial i/o mode b2 b1 b0 0 invalid in clock synchronous serial i/o mode txd, rxd i/o polarity reverse bit (note1) 0 : no reverse 1 : reverse notes 1: usually set to 0 . 2: set a corresponding direction register to "0." note 1: set a corresponding direction register to "0."
104 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP pin name function method of selection txdi (p6 3 , p6 7 , p7 0 ) serial data output serial data input transfer clock output transfer clock input programmable i/o port (outputs dummy data when performing reception only) rxdi (p6 2 , p6 6 , p7 1 ) clki (p6 1 , p6 5 , p7 2 ) internal/external clock select bit (bit 3 at address 03a0 16 , 03a8 16 , 0378 16 ) = 0 internal/external clock select bit (bit 3 at address 03a0 16 , 03a8 16 , 0378 16 ) = 1 port p6 1 , p6 5 and p7 2 direction register (bits 1 and 5 at address 03ee 16 , bit 2 at address 03ef 16 ) = 0 port p6 2 , p6 6 and p7 1 direction register (bits 2 and 6 at address 03ee 16 , bit 1 at address 03ef 16 )= 0 (can be used as an input port when performing transmission only) cts/rts disable bit (bit 4 at address 03a4 16 , 03ac 16 , 037c 16 ) = 0 cts/rts function select bit (bit 2 at address 03a4 16 , 03ac 16 , 037c 16 ) = 0 port p6 0 , p6 4 and p7 3 direction register (bits 0 and 4 at address 03ee 16 , bit 3 at address 03ef 16 ) = 0 cts/rts disable bit (bit 4 at address 03a4 16 , 03ac 16 , 037c 16) = 0 cts/rts function select bit (bit 2 at address 03a4 16 , 03ac 16 , 037c 16 ) = 1 cts/rts disable bit (bit 4 at address 03a4 16 , 03ac 16 , 037c 16 ) = 1 cts input rts output ctsi/rtsi (p6 0 , p6 4 , p7 3 ) table 2.11.4 lists the functions of the input/output pins during clock synchronous serial i/o mode. note that for a period from when the uarti operation mode is selected to when transfer starts, the txdi pin outputs a h . (if the n-channel open-drain is selected, this pin is in floating state.) table 2.11.4 input/output pin functions in clock synchronous serial i/o mode
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 105 rev. 1.0 M306H2MC-XXXFP figure 2.11.11 typical transmit/receive timings in clock synchronous serial i/o mode example of transmit timing (when internal clock is selected) d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 t c t c l k s t o p p e d p u l s i n g b e c a u s e t r a n s f e r e n a b l e b i t = 0 d a t a i s s e t i n u a r t i t r a n s m i t b u f f e r r e g i s t e r t c = t c l k = 2 ( n + 1 ) / f i f i : f r e q u e n c y o f b r g i c o u n t s o u r c e ( f 1 , f 8 , f 3 2 ) n : v a l u e s e t t o b r g i t r a n s f e r c l o c k t r a n s m i t e n a b l e b i t ( t e ) t r a n s m i t b u f f e r e m p t y f l a g ( t l ) c l k i t x d i t r a n s m i t r e g i s t e r e m p t y f l a g ( t x e p t ) h l 0 1 0 1 0 1 c t s i t h e a b o v e t i m i n g a p p l i e s t o t h e f o l l o w i n g s e t t i n g s : i n t e r n a l c l o c k i s s e l e c t e d . c t s f u n c t i o n i s s e l e c t e d . c l k p o l a r i t y s e l e c t b i t = 0 . t r a n s m i t i n t e r r u p t c a u s e s e l e c t b i t = 0 . t r a n s m i t i n t e r r u p t r e q u e s t b i t ( i r ) 0 1 s t o p p e d p u l s i n g b e c a u s e c t s = h t r a n s f e r r e d f r o m u a r t i t r a n s m i t b u f f e r r e g i s t e r t o u a r t i t r a n s m i t r e g i s t e r s h o w n i n ( ) a r e b i t s y m b o l s . c l e a r e d t o 0 w h e n i n t e r r u p t r e q u e s t i s a c c e p t e d , o r c l e a r e d b y s o f t w a r e 1 / f e x t d u m m y d a t a i s s e t i n u a r t i t r a n s m i t b u f f e r r e g i s t e r t r a n s m i t e n a b l e b i t ( t e ) t r a n s m i t b u f f e r e m p t y f l a g ( t l ) c l k i r x d i r e c e i v e c o m p l e t e f l a g ( r l ) r t s i h l 0 1 0 1 0 1 r e c e i v e e n a b l e b i t ( r e ) 0 1 r e c e i v e d a t a i s t a k e n i n t r a n s f e r r e d f r o m u a r t i t r a n s m i t b u f f e r r e g i s t e r t o u a r t i t r a n s m i t r e g i s t e r r e a d o u t f r o m u a r t i r e c e i v e b u f f e r r e g i s t e r t h e a b o v e t i m i n g a p p l i e s t o t h e f o l l o w i n g s e t t i n g s : t r a n s f e r r e d f r o m u a r t i r e c e i v e r e g i s t e r t o u a r t i r e c e i v e b u f f e r r e g i s t e r r e c e i v e i n t e r r u p t r e q u e s t b i t ( i r ) 0 1 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 s h o w n i n ( ) a r e b i t s y m b o l s . m e e t t h e f o l l o w i n g c o n d i t i o n s a r e m e t w h e n t h e c l k c l e a r e d t o 0 w h e n i n t e r r u p t r e q u e s t i s a c c e p t e d , o r c l e a r e d b y s o f t w a r e example of receive timing (when external clock is selected)
106 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP when clk polarity select bit = 1 note 2: the clk pin level when not transferring data is l . d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 0 t x d i r x d i clk i when clk polarity select bit = 0 note 1: the clk pin level when not transferring data is h . d 1 d 2 d 3 d 4 d 5 d 6 d 7 d0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 t x d i r x d i clk i lsb first when transfer format select bit = 0 d0 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 1 d 2 d 3 d 4 d 5 d 6 d 7 t x d i r x d i clk i when transfer format select bit = 1 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 t x d i r x d i clk i msb first note: this applies when the clk polarity select bit = 0 . (1) polarity select function as shown in figure 2.11.12 the clk polarity select bit (bit 6 at addresses 03a4 16 , 03ac 16 , 037c 16 ) allows selection of the polarity of the transfer clock. figure 2.11.12 polarity of transfer clock (2) lsb first/msb first select function as shown in figure 2.11.13, when the transfer format select bit (bit 7 at addresses 03a4 16 , 03ac 16 , 037c 16 ) = 0 , the transfer format is lsb first ; when the bit = 1 , the transfer format is msb first . figure 2.11.13 transfer format
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 107 rev. 1.0 M306H2MC-XXXFP (3) transfer clock output from multiple pins function (uart1) this function allows the setting two transfer clock output pins and choosing one of the two to output a clock by using the clk and clks select bit (bits 4 and 5 at address 03b0 16 ). (see figure 2.11.14) the multiple pins function is valid only when the internal clock is selected for uart1. figure 2.11.14 the transfer clock output from the multiple pins function usage microcomputer t x d 1 (p6 7 ) clks 1 (p6 4 ) clk 1 (p6 5 ) in clk in clk note: this applies when the internal clock is selected and transmission is performed only in clock synchronous serial i/o mode. (4) continuous receive mode if the continuous receive mode enable bit (bits 2 and 3 at address 03b0 16 , bit 5 at address 037d 16 ) is set to 1 , the unit is placed in continuous receive mode. in this mode, when the receive buffer register is read out, the unit simultaneously goes to a receive enable state without having to set dummy data to the transmit buffer register back again. (5) serial data logic switch function (uart2) when the data logic select bit (bit6 at address 037d 16 ) = 1 , and writing to transmit buffer register or reading from receive buffer register, data is reversed. figure 2.11.15 shows the example of serial data logic switch timing. figure 2.11.15 serial data logic switch timing d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 transfer clock txd 2 (no reverse) txd 2 (reverse) h l h l h l when lsb first
108 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP note 1: ??denotes the value 00 16 to ff 16 that is set to the uarti bit rate generator. note 2: f ext is input from the clki pin. note 3: if an overrun error occurs, the uarti receive buffer will have the next data written in. note also that the uarti receive interrupt request bit does not change. item specification transfer data format ?character bit (transfer data): 7 bits, 8 bits, or 9 bits as selected ?start bit: 1 bit ?parity bit: odd, even, or nothing as selected ?stop bit: 1 bit or 2 bits as selected transfer clock ? when internal clock is selected (bit 3 at addresses 03a0 16 , 03a8 16 , 0378 16 = ?? : fi/16(n+1) (note 1) fi = f 1 , f 8 , f 32 ? when external clock is selected (bit 3 at addresses 03a0 16 and 03a8 16 = ?? : f ext /16(n+1) (note 1) (note 2) (do not set external clock for uart2) transmission/reception control _______ _______ _______ _______ ?cts function/rts function/cts, rts function chosen to be invalid transmission start condition ?to start transmission, the following requirements must be met: - transmit enable bit (bit 0 at addresses 03a5 16 , 03ad 16 , 037d 16 ) = ? - transmit buffer empty flag (bit 1 at addresses 03a5 16 , 03ad 16 , 037d 16 ) = ? _______ _______ - when cts function selected, cts input level = ? reception start condition ?to start reception, the following requirements must be met: - receive enable bit (bit 2 at addresses 03a5 16 , 03ad 16 , 037d 16 ) = 1 - start bit detection interrupt request ?when transmitting generation timing - t ransmit interrupt cause select bits (bits 0,1 at address 03b0 16 , bit4 at address 037d 16 ) = ?? interrupts requested when data transfer from uarti transfer buffer register to uarti transmit register is completed - transmit interrupt cause select bits (bits 0, 1 at address 03b0 16 , bit4 at address 037d 16 ) = ?? interrupts requested when data transmission from uarti transfer register is completed ? when receiving - interrupts requested when data transfer from uarti receive register to uarti receive buffer register is completed error detection ?overrun error (note 3) this error occurs when the next data is ready before contents of uarti receive buffer register are read out ?framing error this error occurs when the number of stop bits set is not detected ?parity error this error occurs when if parity is enabled, the number of 1? in parity and character bits does not match the number of 1? set ?error sum flag this flag is set (= 1) when any of the overrun, framing, and parity errors is encountered 2.11.3 clock asynchronous serial i/o (uart) mode the uart mode allows transmitting and receiving data after setting the desired transfer rate and transfer data format. tables 2.11.5 and 2.11.6 list the specifications of the uart mode. figure 2.11.16 shows the uarti transmit/receive mode register. table 2.11.5 specifications of uart mode (1)
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 109 rev. 1.0 M306H2MC-XXXFP table 2.11.6 specifications of uart mode (2) item specification select function ?sleep mode selection (uart0, uart1) this mode is used to transfer data to and from one of multiple slave micro- computers serial data logic switch (uart2) this function is reversing logic value of transferring data. start bit, parity bit and stop bit are not reversed. ? x d, r x d i/o polarity switch (uart2) this function is reversing t x d port output and r x d port input. all i/o data level is reversed.
110 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP figure 2.11.16 uarti transmit/receive mode register in uart mode symbol address when reset uimr(i=0,1) 03a0 16 , 03a8 16 00 16 ckdir uarti transmit / receive mode registers internal / external clock select bit stps pry prye slep 0 : internal clock 1 : external clock (note) bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 smd0 smd1 smd2 serial i/o mode select bit b2 b1 b0 0 : one stop bit 1 : two stop bits 0 : parity disabled 1 : parity enabled 0 : sleep mode deselected 1 : sleep mode selected 1 0 0 : transfer data 7 bits length 1 0 1 : transfer data 8 bits length 1 1 0 : transfer data 9 bits length valid when bit 6 = 1 0 : odd parity 1 : even parity stop bit length select bit odd / even parity select bit parity enable bit sleep select bit symbol address when reset u2mr 0378 16 00 16 ckdir uart2 transmit / receive mode register internal / external clock select bit stps pry prye iopol must always be fixed to 0 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 smd0 smd1 smd2 serial i/o mode select bit b2 b1 b0 0 : one stop bit 1 : two stop bits 0 : parity disabled 1 : parity enabled 0 : no reverse 1 : reverse 1 0 0 : transfer data 7 bits length 1 0 1 : transfer data 8 bits length 1 1 0 : transfer data 9 bits length valid when bit 6 = 1 0 : odd parity 1 : even parity stop bit length select bit odd / even parity select bit parity enable bit txd, rxd i/o polarity reverse bit (note) note: usually set to 0 . note: set a corresponding direction register to "0."
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 111 rev. 1.0 M306H2MC-XXXFP table 2.11.7 lists the functions of the input/output pins during uart mode. note that for a period from when the uarti operation mode is selected to when transfer starts, the txdi pin outputs a h . (if the n-channel open-drain is selected, this pin is in floating state.) table 2.11.7 input/output pin functions in uart mode pin name function method of selection txdi (p6 3 , p6 7 , p7 0 ) serial data output serial data input programmable i/o port transfer clock input programmable i/o port rxdi (p6 2 , p6 6 , p7 1 ) clki (p6 1 , p6 5 , p7 2 ) internal/external clock select bit (bit 3 at address 03a0 16 , 03a8 16 , 0378 16 ) = 0 internal/external clock select bit (bit 3 at address 03a0 16 , 03a8 16 ) = 1 port p6 1 , p6 5 direction register (bits 1 and 5 at address 03ee 16 ) = 0 (do not set external clock for uart2) port p6 2 , p6 6 and p7 1 direction register (bits 2 and 6 at address 03ee 16 , bit 1 at address 03ef 16 )= 0 (can be used as an input port when performing transmission only) cts/rts disable bit (bit 4 at address 03a4 16 , 03ac 16 , 037c 16 ) = 0 cts/rts function select bit (bit 2 at address 03a4 16 , 03ac 16 , 037c 16 ) = 0 port p6 0 , p6 4 and p7 3 direction register (bits 0 and 4 at address 03ee 16 , bit 3 at address 03ef 16 ) = 0 cts/rts disable bit (bit 4 at address 03a4 16 , 03ac 16 , 037c 16) = 0 cts/rts function select bit (bit 2 at address 03a4 16 , 03ac 16 , 037c 16 ) = 1 cts/rts disable bit (bit 4 at address 03a4 16 , 03ac 16 , 037c 16 ) = 1 cts input rts output ctsi/rtsi (p6 0 , p6 4 , p7 3 )
112 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP transmit enable bit(te) transmit buffer empty flag(ti) transmit register empty flag (txept) start bit parity bit txdi ctsi the above timing applies to the following settings : parity is enabled. one stop bit. cts function is selected. transmit interrupt cause select bit = 1 . 1 0 1 l h 0 1 tc = 16 (n + 1) / fi or 16 (n + 1) / f ext fi : frequency of brgi count source (f 1 , f 8 , f 32 ) f ext : frequency of brgi count source (external clock) n : value set to brgi transmit interrupt request bit (ir) 0 1 cleared to 0 when interrupt request is accepted, or cleared by software transmit enable bit(te) transmit buffer empty flag(ti) txdi transmit register empty flag (txept) 0 1 0 1 0 1 the above timing applies to the following settings : parity is disabled. two stop bits. cts function is disabled. transmit interrupt cause select bit = 0 . transfer clock tc tc = 16 (n + 1) / fi or 16 (n + 1) / f ext fi : frequency of brgi count source (f 1 , f 8 , f 32 ) f ext : frequency of brgi count source (external clock) n : value set to brgi transmit interrupt request bit (ir) 0 1 shown in ( ) are bit symbols. shown in ( ) are bit symbols. tc transfer clock d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 sp st p sp d 0 d 1 st stopped pulsing because transmit enable bit = 0 stop bit transferred from uarti transmit buffer register to uarti transmit register start bit the transfer clock stops momentarily as cts is h when the stop bit is checked. the transfer clock starts as the transfer starts immediately cts changes to l . data is set in uarti transmit buffer register d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st sp d 8 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st d 8 d 0 d 1 st sp sp transferred from uarti transmit buffer register to uarti transmit register stop bit stop bit data is set in uarti transmit buffer register. 0 sp cleared to 0 when interrupt request is accepted, or cleared by software example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit) example of transmit timing when transfer data is 9 bits long (parity disabled, two stop bits) figure 2.11.17 typical transmit timings in uart mode(uart0,uart1)
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 113 rev. 1.0 M306H2MC-XXXFP figure 2.11.18 typical transmit timings in uart mode(uart2) d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p start bit parity bit cleared to 0 when interrupt request is accepted, or cleared by software d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p tc sp stop bit data is set in uart2 transmit buffer register transferred from uart2 transmit buffer register to uarti transmit register sp transmit enable bit(te) transmit buffer empty flag(ti) transmit register empty flag (txept) 0 1 0 1 0 1 transmit interrupt request bit (ir) 0 1 transfer clock txd 2 the above timing applies to the following settings : parity is enabled. one stop bit. transmit interrupt cause select bit = 1 . tc = 16 (n + 1) / fi fi : frequency of brg2 count source (f 1 , f 8 , f 32 ) n : value set to brg2 shown in ( ) are bit symbols. note note: the transmit is started with overflow timing of brg after having written in a value at the transmit buffer in the above t iming. example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit)
114 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP s t : s t a r t b i t p : e v e n p a r i t y s p : s t o p b i t d 0 d 1d 2d 3d 4d 5d 6d 7p s p s t s p s td 3 d 4 d 5 d 6 d 7 p d 0 d 1 d 2 t r a n s f e r c l o c k t x d 2 ( n o r e v e r s e ) t x d 2 ( r e v e r s e ) h l h l h l w h e n l s b f i r s t , p a r i t y e n a b l e d , o n e s t o p b i t figure 2.11.20 timing for switching serial data logic example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit) d 0 s t a r t b i t s a m p l e d l r e c e i v e d a t a t a k e n i n b r g i c o u n t s o u r c e r e c e i v e e n a b l e b i t r x d i t r a n s f e r c l o c k r e c e i v e c o m p l e t e f l a g r t s i s t o p b i t 1 0 0 1 h l t h e a b o v e t i m i n g a p p l i e s t o t h e f o l l o w i n g s e t t i n g s : p a r i t y i s d i s a b l e d . o n e s t o p b i t . r e c e i v e i n t e r r u p t r e q u e s t b i t 0 1 t r a n s f e r r e d f r o m u a r t i r e c e i v e r e g i s t e r t o u a r t i r e c e i v e b u f f e r r e g i s t e r r e c e p t i o n t r i g g e r e d w h e n t r a n s f e r c l o c k i s g e n e r a t e d b y f a l l i n g e d g e o f s t a r t b i t d 7 d 1 c l e a r e d t o 0 w h e n i n t e r r u p t r e q u e s t i s a c c e p t e d , o r c l e a r e d b y s o f t w a r e figure 2.11.19 typical receive timing in uart mode (1) sleep mode (uart0, uart1) this mode is used to transfer data between specific microcomputers among multiple microcomputers connected using uarti. the sleep mode is selected when the sleep select bit (bit 7 at addresses 03a0 16 , 03a8 16 ) is set to 1 during reception. in this mode, the unit performs receive operation when the msb of the received data = 1 and does not perform receive operation when the msb = 0 . (2) function for switching serial data logic (uart2) when the data logic select bit (bit 6 of address 037d 16 ) is assigned 1, data is inverted in writing to the transmission buffer register or reading the reception buffer register. figure 2.11.20 shows the ex- ample of timing for switching serial data logic.
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 115 rev. 1.0 M306H2MC-XXXFP (3) txd, rxd i/o polarity reverse function (uart2) this function is to reverse t x d pin output and r x d pin input. the level of any data to be input or output (including the start bit, stop bit(s), and parity bit) is reversed. set this function to 0 (not to reverse) for usual use. (4) bus collision detection function (uart2) this function is to sample the output level of the t x d pin and the input level of the r x d pin at the rising edge of the transfer clock; if their values are different, then an interrupt request occurs. figure 2.11.21 shows the example of detection timing of a buss collision (in uart mode). figure 2.11.21 detection timing of a bus collision (in uart mode) s t : s t a r t b i t s p : s t o p b i t s t s t s p s p t r a n s f e r c l o c k t x d 2 r x d 2 b u s c o l l i s i o n d e t e c t i o n i n t e r r u p t r e q u e s t s i g n a l h l h l h l 1 0 b u s c o l l i s i o n d e t e c t i o n i n t e r r u p t r e q u e s t b i t 1 0
116 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP item specification transfer data format transfer data 8-bit uart mode (bit 2 through bit 0 of address 0378 16 = 101 2 ) one stop bit (bit 4 of address 0378 16 = 0 ) with the direct format chosen set parity to even (bit 5 and bit 6 of address 0378 16 = 1 and 1 respectively) set data logic to direct (bit 6 of address 037d 16 = 0 ). set transfer format to lsb (bit 7 of address 037c 16 = 0 ). with the inverse format chosen set parity to odd (bit 5 and bit 6 of address 0378 16 = 0 and 1 respectively) set data logic to inverse (bit 6 of address 037d 16 = 1 ) set transfer format to msb (bit 7 of address 037c 16 = 1 ) transfer clock with the internal clock chosen (bit 3 of address 0378 16 = 0 ) : fi / 16 (n + 1) (note 1) : fi=f 1 , f 8 , f 32 (do not set external clock) transmission / reception control _______ _______ disable the cts and rts function (bit 4 of address 037c 16 = 1 ) other settings the sleep mode select function is not available for uart2 set transmission interrupt factor to transmission completed (bit 4 of address 037d 16 = 1 ) transmission start condition to start transmission, the following requirements must be met: - transmit enable bit (bit 0 of address 037d 16 ) = 1 - transmit buffer empty flag (bit 1 of address 037d 16 ) = 0 r eceptio n start condition to start reception, the following requirements must be met: - reception enable bit (bit 2 of address 037d 16 ) = 1 - detection of a start bit when transmitting when data transmission from the uart2 transfer register is completed (bit 4 of address 037d 16 = 1 ) when receiving when data transfer from the uart2 receive register to the uart2 receive buffer register is completed error detection overrun error (see the specifications of clock-asynchronous serial i/o) (note 2) framing error (see the specifications of clock-asynchronous serial i/o) parity error (see the specifications of clock-asynchronous serial i/o) - on the reception side, an l level is output from the t x d 2 pin by use of the parity error signal output function (bit 7 of address 037d 16 = 1 ) when a parity error is detected - on the transmission side, a parity error is detected by the level of input to the r x d 2 pin when a transmission interrupt occurs the error sum flag (see the specifications of clock-asynchronous serial i/o) 2.11.4 clock-asynchronous serial i/o mode (compliant with the sim interface) the sim interface is used for connecting the microcomputer with a memory card or the like; adding some extra settings in uart2 clock-asynchronous serial i/o mode allows the user to effect this func- tion. table 2.11.8 shows the specifications of clock-asynchronous serial i/o mode (compliant with the sim interface). interrupt request generation timing table 2.11.8 specifications of clock-asynchronous serial i/o mode (compliant with the sim interface) note 1: n denotes the value 00 16 to ff 16 that is set to the uarti bit rate generator. note 2: if an overrun error occurs, the uart2 receive buffer will have the next data written in. note also that the uart2 receive interrupt request bit does not change.
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 117 rev. 1.0 M306H2MC-XXXFP figure 2.11.22 typical transmit/receive timing in uart mode (compliant with the sim interface) transmit enable bit(te) transmit buffer empty flag(ti) transmit register empty flag (txept) d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p start bit parity bit the above timing applies to the following settings : parity is enabled. one stop bit. transmit interrupt cause select bit = 1 . 0 1 0 1 0 1 tc = 16 (n + 1) / fi fi : frequency of brg2 count source (f 1 , f 8 , f 32 ) n : value set to brg2 transmit interrupt request bit (ir) 0 1 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p shown in ( ) are bit symbols. tc transfer clock sp stop bit data is set in uart2 transmit buffer register sp a l level returns from txd 2 due to the occurrence of a parity error. the level is detected by the interrupt routine. the level is detected by the interrupt routine receive enable bit (re) receive complete flag (ri) d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p start bit parity bit rxd 2 the above timing applies to the following settings : parity is enabled. one stop bit. transmit interrupt cause select bit = 0 . 0 1 0 1 tc = 16 (n + 1) / fi fi : frequency of brg2 count source (f 1 , f 8 , f 32 ) n : value set to brg2 receive interrupt request bit (ir) 0 1 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p sp shown in ( ) are bit symbols. tc transfer clock sp stop bit a l level returns from txd 2 due to the occurrence of a parity error. txd 2 read to receive buffer read to receive buffer d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p signal conductor level (note 2) d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p sp sp d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p sp sp txd 2 rxd 2 signal conductor level (note 2) note 2: equal in waveform because txd 2 and rxd 2 are connected. transferred from uart2 transmit buffer register to uart2 transmit register cleared to 0 when interrupt request is accepted, or cleared by software cleared to 0 when interrupt request is accepted, or cleared by software note 1: the transmit is started with overflow timing of brg after having written in a value at the transmit buffer in the above timing. note1
118 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP (1) parity error signal output function if a parity error is detected when the error signal output enable bit (address 037d 16 , bit 7) has been set to 1 , a low-level signal can be output from the txd 2 pin. also, when operating in transmit mode, a transmit-complete interrupt is generated a half transfer clock cycle later than when the error signal output enable bit (address 037d 16 , bit 7) is set to 0 . therefore, a parity error signal can be detected in the transmit-complete interrupt program. figure 2.11.23 shows the timing at which a parity error signal is output. st : start bit p : even parity sp : stop bit d0 d1 d2 d3 d4 d5 d6 d7 p sp st hi-z transfer clock rxd 2 txd 2 receive complete flag h l h l h l 1 lsb first 0 p : even parity d0 d1 d2 d3 d4 d5 d6 d7 p transfer clcck txd 2 (direct) txd 2 (inverse) d7 d6 d5 d4 d3 d2 d1 d0 p figure 2.11.23 output timing of the parity error signal (2) direct format/inverse format connecting the sim card allows you to switch between direct format and inverse format. if you choose the direct format, d0 data is output from txd2. if you choose the inverse format, d7 data is inverted and output from txd2. figure 2.11.24 shows the sim interface format. figure 2.11.24 sim interface format
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 119 rev. 1.0 M306H2MC-XXXFP figure 2.11.25 shows the example of connecting the sim interface. connect t x d 2 and r x d 2 and apply pull-up. figure 2.11.25 connecting the sim interface microcomputer sim card txd 2 rxd 2
120 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP 2.11.5 uart2 special mode register the uart2 special mode register (address 0377 16 ) is used to control uart2 in various ways. figure 2.11.26 shows the uart2 special mode register. bit 0 of the uart special mode register (0377 16 ) is used as the i 2 c mode selection bit. setting ??in the i 2 c mode select bit (bit 0) goes the circuit to achieve the i 2 c bus interface effective. since this function uses clock-synchronous serial i/o mode, set this bit to ??in uart mode. figure 2.11.26 uart2 special mode register uart2 special mode register symbol address when reset u2smr 0377 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol w r function (during uart mode) function (during clock synchronous serial i/o mode) abscs acse sss i c mode selection bit bus busy flag 0 : stop condition detected 1 : start condition detected scll sync output enable bit bus collision detect sampling clock select bit arbitration lost detecting flag control bit 0 : normal mode 1 : i c mode 0 : update per bit 1 : update per byte iicm abc bbs lsyn 0 : ordinary 1 : falling edge of rxd2 0 : disabled 1 : enabled transmit start condition select bit must always be 0 0 : rising edge of transfer clock 1 : underflow signal of timer a0 auto clear function select bit of transmit enable bit 0 : no auto clear function 1 : auto clear at occurrence of bus collision must always be 0 must always be 0 must always be 0 must always be 0 must always be 0 must always be 0 notes 1: nothing but "0" may be written. 2: do not write "1" except at i 2 c mode. must always be 0 at normal mode. bit 7 to bit5 (dl2 to dl0 = sda digital delay value setting bit) of uart2 special mode register 3 (u2smr3/address 0375 16 ) are initialized and become 000 when this bit is "0", analog delay circuit is selected. reading and writing u2smr are enable when sdds = "0" . 3: delaying ; only analog delay value when analog delay is selected, and only digital delay value when digital delay is selected. (note 1) 2 2 sdds sda digital delay select bit (notes 2 and 3) 0 : selects analog delay output 1 : selects digital delay output (must always be 0 except at i 2 c mode) must always be 0 uart2 special mode register 3 (i 2 c bus exclusive register) symbol address when reset u2smr3 0375 16 indeterminate b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol function (i 2 c bus exclusive) sda digital delay value set bit b7 b6 b5 dl0 dl1 dl2 (initializing value is "00 16 " at sdds = "1") nothing is assigned. in an attempt to write to this bit, write 0 . the value, if read, turns out to be 0 . 0 is read out when sdds = 1. w r notes 1: reading and writing is possible when bit7 (sdds = sda digital delay selection bit) of uart2 special mode register (u2smr/address 0377 16 ) is "1". when set sdds = "1" and read out initialized value of uart2 special mode register 3(u2smr3), this value is "00 16 ".when set sdds = "1" and write to uart2 special mode register 3(u2smr3), set "0" to bit 0 to bit 4. when sdds = "0", writing is enable. when read out, this value is indeterminate. 2: when sdds = "0" , this bit is initialized and become "000", selected analog delay circuit. this bit is become "000" after end reset released, and selected analog delay circuit. reading out is possible when only sdds = "1". when sdds = "0", value which was read out is indeterminate. 3: delaying ; only analog delay value when analog delay is selected, and only digital delay value when digital delay is selected. 4: delay level depends on scl pin and sda pin. and, when use external clock, delay is increase around 100ns. so test first, and use this. 0 0 0 : selects analog delay 0 0 1 : 1 2 cycle of 1/f (xin)(digital delay) 0 1 0 : 2 3 cycle of 1/f (xin)(digital delay) 0 1 1 : 3 4 cycle of 1/f (xin)(digital delay) 1 0 0 : 4 5 cycle of 1/f (xin)(digital delay) 1 0 1 : 5 6 cycle of 1/f (xin)(digital delay) 1 1 0 : 6 7 cycle of 1/f (xin)(digital delay) 1 1 1 : 7 8 cycle of 1/f (xin)(digital delay)
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 121 rev. 1.0 M306H2MC-XXXFP figure 2.11.27 functional block diagram for i 2 c mode function normal mode i 2 c mode (note 1) factor of interrupt number 15 (note 2) uart2 transmission no acknowledgment detection (nack) factor of interrupt number 16 (note 2) uart2 reception start condition detection or stop condition detection uart2 transmission output delay not delayed delayed (digital / analog selection is possible) p7 0 at the time when uart2 is in use txd 2 (output) sda (input/output) (note 3) p7 1 at the time when uart2 is in use rxd 2 (input) scl (input/output) p7 2 at the time when uart2 is in use clk 2 p7 2 dma1 factor at the time when 1 1 0 1 is assigned to the dma request factor selection bits uart2 reception acknowledgment detection (ack) noise filter width 15ns 50ns reading p7 1 reading the terminal when 0 is assigned to the direction register reading the terminal regardless of the value of the direction register 1 2 3 4 5 6 7 8 9 note 1: make the settings given below when i 2 c mode is in use. set 0 1 0 in bits 2, 1, 0 of the uart2 transmission/reception mode register. disable the rts/cts function. choose the msb first function. note 2: follow the steps given below to switch from a factor to another. 1. disable the interrupt of the corresponding number. 2. switch from a factor to another. 3. reset the interrupt request flag of the corresponding number. 4. set an interrupt level of the corresponding number. note 3: set an initial value of sda transmission output when serial i/o is invalid. factor of interrupt number 10 (note 2) bus collision detection acknowledgment detection (ack) 10 initial value of uart2 output h level (when 0 is assigned to the clk polarity select bit) the value set in latch p7 0 when the port is selected 11 table 2.11.9 features in i 2 c mode i i c m = 1 a n d i i c m 2 = 0 i i c m = 0 o r i i c m 2 = 1 t o d m a 0 i / o n o i z e f i l t e r p 7 1 / r x d 2 / s c l r e c e p t i o n r e g i s t e r c l k c o n t r o l u a r t 2 n o i z e f i l t e r u a r t 2 p 7 2 / c l k 2 d t q d t q u a r t 2 u a r t 2 r i i c m = 1 i i c m = 0 i i c m = 0 i i c m = 1 i i c m = 1 i i c m = 0 s r q s w c f a l l i n g o f 9 t h p u l s e s w c 2 s t a r t c o n d i t i o n d e t e c t i o n s t o p c o n d i t i o n d e t e c t i o n f a l l i n g e d g e d e t e c t i o n l - s y n c h r o n o u s o u t p u t e n a b l i n g b i t d a t a b u s s e l e c t o r i n t e r n a l c l o c k e x t e r n a l c l o c k s e l e c t o r i / o t i m e r p o r t r e a d i n g b u s b u s y u a r t 2 r e c e p t i o n / a c k i n t e r r u p t r e q u e s t d m a 1 r e q u e s t n a c k a c k i i c m = 1 i i c m = 0 * w i t h i i c m s e t t o 1 , t h e p o r t t e r m i n a l i s t o b e r e a d a b l e e v e n i f 1 i s a s s i g n e d t o p 7 1 o f t h e d i r e c t i o n r e g i s t e r . b u s c o l l i s i o n d e t e c t i o n 9 t h p u l s e b u s c o l l i s i o n / s t a r t , s t o p c o n d i t i o n d e t e c t i o n i n t e r r u p t r e q u e s t n o i z e f i l t e r d t q i i c m = 1 a n d i i c m 2 = 0 i i c m = 0 o r i i c m 2 = 1 t o d m a 0 , d m a 1 u a r t 2 t r a n s m i s s i o n / n a c k i n t e r r u p t r e q u e s t i / o u a r t 2 p 7 0 / t x d 2 / s d a s e l e c t o r t i m e r t r a n s m i s s i o n r e g i s t e r a r b i t r a t i o n a n a l o g d e l a y u a r t 2 i i c m = 1 ( s d d s = 0 ) o r d l = 0 0 0 ( s d d s = 1 ) a l s s d h i i i c m = 0 o r d l = 0 0 0 ( s d d s = 1 ) s d d s = 1 a n d d l = 0 0 0 d i g i t a l d e l a y ( d i v i e r ) s d d s = 0 o r d l = 0 0 0 q ( p o r t p 7 1 o u t p u t d a t a l a t c h ) p 7 0 t h r o u g h p 7 2 c o n f o r m i n g t o t h e s i m p l i f i e d i 2 c b u s
122 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP figure 2.11.27 hows the functional block diagram for i 2 c mode. setting 1 in the i 2 c mode selection bit (iicm) causes ports p7 0 , p7 1 , and p7 2 to work as data transmission-reception terminal sda, clock input-output terminal scl, and port p7 2 respectively. a delay circuit is added to the sda transmission output, so the sda output changes after scl fully goes to l . can select analog delay or digital delay by sda digital delay selection bit (7 bit of address 0377 16 ). when select digital delay, can select delay to 2 cycle to 8 cycle of f1 by uart2 special mode register 3 (address 0375 16 ) . functions changed by i 2 c mode selection bit 2 is shown in below. table 2.11.10 delay circuit selection condition w h e n s e l e c t d i g i t a l d e l a y , a n a l o g d e l a y i s n o t a d d e d . o n l y d i g i t a l d e l a y . 0 0 1 t o 1 1 1 w h e n s e l e c t d l = " 0 0 0 " , a n a l o g d e l a y i s c h o s e n r e g a r d l e s s o f t h e v a l u e o f s d d s . w h e n s d d s = " 0 " , d l i s i n i t i a l i z e d a n d d l = " 0 0 0 " . 0 0 0 ( 0 0 0 ) 1 0 1 1 1 d e l a y c i r c u i t i s n o t s e l e c t e d w h e n i i c m = " 0 " . b u t , m u s t s e t s d d s = " 0 " w h e n i i c m = " 0 " . 0 0 ( 0 0 0 ) i i c m s d d sd l r e g i s t e r v a l u e c o n t e n t s d i g i t a l d e l a y s e l e c t i o n a n a l o g d e l a y s e l e c t i o n n o d e l a y an attempt to read port p7 1 (scl) results in getting the terminal s level regardless of the content of the port direction register. the initial value of sda transmission output in this mode goes to the value set in port p7 0 . the interrupt factors of the bus collision detection interrupt, uart2 transmission interrupt, and of uart2 reception interrupt turn to the start/stop condition detection interrupt, acknowledgment non-detection interrupt, and acknowledgment detection interrupt respectively. the start condition detection interrupt refers to the interrupt that occurs when the falling edge of the sda terminal (p7 0 ) is detected with the scl terminal (p7 1 ) staying h . the stop condition detection interrupt refers to the interrupt that occurs when the rising edge of the sda terminal (p7 0 ) is detected with the scl terminal (p7 1 ) staying h . the bus busy flag (bit 2 of the uart2 special mode register) is set to 1 by the start condition detection, and set to 0 by the stop condition detection. the acknowledgment non-detection interrupt refers to the interrupt that occurs when the sda terminal level is detected still staying h at the rising edge of the 9th transmission clock. the acknowledgment detection interrupt refers to the interrupt that occurs when sda terminal s level is detected already went to l at the 9th transmission clock. also, assigning 1101(uart2 reception) to the dma1 request factor select bits provides the means to start up the dma transfer by the effect of acknowledgment detection. bit 1 of the uart2 special mode register (0377 16 ) is used as the arbitration loss detecting flag control bit. arbitration means the act of detecting the nonconformity between transmission data and sda terminal data at the timing of the scl rising edge. this detecting flag is located at bit 11 of the uart2 reception buffer register (037f 16 , 037e 16 ), and 1 is set in this flag when nonconformity is detected. use the arbitration lost detecting flag control bit to choose which way to use to update the flag, bit by bit or byte by byte. when setting this bit to 1 and updated the flag byte by byte if nonconformity is detected, the arbitration lost detecting flag is set to 1 at the falling edge of the 9th transmission clock. if update the flag byte by byte, must judge and clear ( 0 ) the arbitration lost detecting flag after com- pleting the first byte acknowledge detect and before starting the next one byte transmission. bit 3 of the uart2 special mode register is used as scl- and l-synchronous output enable bit. setting this bit to 1 goes the p7 1 data register to 0 in synchronization with the scl terminal level going to l .
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 123 rev. 1.0 M306H2MC-XXXFP 1. bus collision detect sampling clock select bit (bit 4 of the uart2 special mode register) 0: rising edges of the transfer clock clk timer a0 1: timer a0 overflow 2. auto clear function select bit of transmt enable bit (bit 5 of the uart2 special mode register) clk txd/rxd bus collision detect interrupt request bit transmit enable bit 3. transmit start condition select bit (bit 6 of the uart2 special mode register) clk txd enabling transmission clk txd rxd with "1: falling edge of rxd 2 " selected 0: in normal state txd/rxd figure 2.11.28 some other functions added some other functions added are explained here. figure 2.11.28 shows their workings. bit 4 of the uart2 special mode register is used as the bus collision detect sampling clock select bit. the bus collision detect interrupt occurs when the rxd2 level and txd2 level do not match, but the nonconformity is detected in synchronization with the rising edge of the transfer clock signal if the bit is set to 0 . if this bit is set to 1 , the nonconformity is detected at the timing of the overflow of timer a0 rather than at the rising edge of the transfer clock. bit 5 of the uart2 special mode register is used as the auto clear function select bit of transmit enable bit. setting this bit to 1 automatically resets the transmit enable bit to 0 when 1 is set in the bus collision detect interrupt request bit (nonconformity). bit 6 of the uart2 special mode register is used as the transmit start condition select bit. setting this bit to 1 starts the txd transmission in synchronization with the falling edge of the rxd terminal.
124 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP s y m b o la d d r e s sw h e n r e s e t u 2 s m r 20 3 7 6 1 6 0 0 1 6 b 7b 6b 5b 4b 3b 2b 1b 0 b i t n a m e b i t s y m b o l w r f u n c t i o n s t a c s w c 2 s d h i i c m o d e s e l e c t i o n b i t 2 s c l w a i t o u t p u t b i t0 : d i s a b l e d 1 : e n a b l e d s d a o u t p u t s t o p b i t u a r t 2 i n i t i a l i z a t i o n b i t c l o c k - s y n c h r o n o u s b i t r e f e r t o t a b l e 2 . 1 1 . 1 1 0 : d i s a b l e d 1 : e n a b l e d i i c m 2 c s c s w c a l s0 : d i s a b l e d 1 : e n a b l e d s d a o u t p u t d i s a b l e b i t s c l w a i t o u t p u t b i t 2 0 : e n a b l e d 1 : d i s a b l e d ( h i g h i m p e d a n c e ) 0 : d i s a b l e d 1 : e n a b l e d 0 : u a r t 2 c l o c k 1 : 0 o u t p u t 2 s h t cs t a r t / s t o p c o n d i t i o n c o n t r o l b i t s e t t h i s b i t t o " 1 " i n i 2 c m o d e ( r e f e r t o t a b l e 2 . 1 1 . 1 2 ) u a r t 2 s p e c i a l m o d e r e g i s t e r 2 figure 2.11.29 uart2 special mode register 2 2.11.6 uart2 special mode register 2 uart2 special mode register 2 (address 0376 16 ) is used to further control uart2 in i 2 c mode. figure 2.11.29 shows the uart2 special mode register 2.
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 125 rev. 1.0 M306H2MC-XXXFP bit 0 of the uart2 special mode register 2 (address 0376 16 ) is used as the i 2 c mode selection bit 2. table 2.11.11 shows the types of control to be changed by i 2 c mode selection bit 2 when the i 2 c mode selection bit is set to "1". table 2.11.12 shows the timing characteristics of detecting the start condition and the stop condition. set the start/stop condition control bit (bit 7 of uart2 special mode register 2) to "1" in i 2 c mode. function iicm2 = 1 iicm2 = 0 factor of interrupt number 15 no acknowledgment detection (nack) uart2 transmission (the rising edge of the final bit of the clock) factor of interrupt number 16 acknowledgment detection (ack) uart2 reception (the falling edge of the final bit of the clock) dma1 factor at the time when 1 1 0 1 is assigned to the dma request factor selection bits acknowledgment detection (ack) uart2 reception (the falling edge of the final bit of the clock) timing for transferring data from the uart2 reception shift register to the reception buffer. the rising edge of the final bit of the reception clock the falling edge of the final bit of the reception clock timing for generating a uart2 reception/ack interrupt request the rising edge of the final bit of the reception clock the falling edge of the final bit of the reception clock 1 2 3 4 5 3 to 6 cycles < duration for setting-up (note2) 3 to 6 cycles < duration for holding (note2) note 1 : when the start/stop condition count bit is "1" . note 2 : "cycles" is in terms of the input oscillation frequency f(x in ) of the main clock. duration for setting up duration for holding scl sda (start condition) sda (stop condition) table 2.11.11 functions changed by i 2 c mode selection bit 2 table 2.11.12 timing characteristics of detecting the start condition and the stop condition(note1)
126 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP p7 0 /txd 2 /sda p7 1 /rxd 2 /scl clk control p7 2 /clk 2 falling edge detection uart2 reception/ack interrupt request, dma1 request to dma0, dma1 to dma0 i/o timer uart2 timer uart2 iicm=1 (sdds=0) or dl=000 (sdds=1) iicm=0 or iicm2=1 iicm=1 and iicm2=0 sdhi noize filter timer uart2 uart2 i/o d t q d t q d t q nack ack uart2 uart2 iicm=1 iicm=0 iicm=0 iicm=1 iicm=1 iicm=0 s r q iicm=1 iicm=0 i/o r q als iicm=0 or dl 000 (sdds=1) sdds=0 or dl=000 sdds=1 and dl 000 swc2 falling edge of 9 bit swc iicm=1 and iicm2=0 iicm=0 or iicm2=1 selector selector selector noize filter noize filter * with iicm set to 1, the port terminal is to be readable even if 1 is assigned to p7 1 of the direction register. port reading external clock internal clock 9th pulse bus collision detection bus collision/start, stop condition detection interrupt request uart2 transmission/ nack interrupt request start condition detection stop condition detection l-synchronous output enabling bit (port p7 1 output data latch) data bus reception register bus busy transmission register arbitration analog delay digital delay (divider) p7 0 through p7 2 conforming to the simplified i 2 c bus figure 2.11.30 functional block diagram for i 2 c mode functions available in i 2 c mode are shown in figure 2.11.30 a functional block diagram. bit 3 of the uart2 special mode register 2 (address 0376 16 ) is used as the sda output stop bit. setting this bit to "1" causes an arbitration loss to occur, and the sda pin turns to high-impedance state the instant when the arbitration loss detection flag is set to "1". bit 1 of the uart2 special mode register 2 (address 0376 16 ) is used as the clock synchronization bit. with this bit set to "1" at the time when the internal scl is set to "h", the internal scl turns to "l" if the falling edge is found in the scl pin; and the baud rate generator reloads the set value, and start counting within the "l" interval. when the internal scl changes from "l" to "h" with the scl pin set to "l", stops counting the baud rate generator, and starts counting it again when the scl pin turns to "h". due to this function, the uart2 transmission-reception clock becomes the logical product of the signal flowing through the internal scl and that flowing through the scl pin. this function operates over the period from the moment earlier by a half cycle than falling edge of the uart2 first clock to the rising edge of the ninth bit. to use this function, choose the internal clock for the transfer clock. bit 2 of the uart2 special mode register 2 (0376 16 ) is used as the scl wait output bit. setting this bit to "1" causes the scl pin to be fixed to "l" at the falling edge of the ninth bit of the clock. setting this bit to "0" frees the output fixed to "l".
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 127 rev. 1.0 M306H2MC-XXXFP bit 4 of the uart2 special mode register 2 (address 0376 16 ) is used as the uart2 initialization bit. setting this bit to "1", and when the start condition is detected, the microcomputer operates as follows. (1) the transmission shift register is initialized, and the content of the transmission register is trans- ferred to the transmission shift register. this starts transmission by dealing with the clock entered next as the first bit. the uart2 output value, however, doesn t change until the first bit data is output after the entrance of the clock, and remains unchanged from the value at the moment when the microcomputer detected the start condition. (2) the reception shift register is initialized, and the microcomputer starts reception by dealing with the clock entered next as the first bit. (3) the scl wait output bit turns to "1". this turns the scl pin to "l" at the falling edge of the ninth bit of the clock. starting to transmit/receive signals to/from uart2 using this function doesn t change the value of the transmission buffer empty flag. to use this function, choose the external clock for the transfer clock. bit 5 of the uart2 special mode register 2 (0376 16 ) is used as the scl pin wait output bit 2. setting this bit to "1" with the serial i/o specified allows the user to forcibly output an "l" from the scl pin even if uart2 is in operation. setting this bit to "0" frees the "l" output from the scl pin, and the uart2 clock is input/output. bit 6 of the uart2 special mode register 2 (0376 16 ) is used as the sda output enable bit. setting this bit to "1" forces the sda pin to turn to the high-impedance state. refrain from changing the value of this bit at the rising edge of the uart2 transfer clock. there can be instances in which arbitration lost detection flag is turned on.
128 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP s i/oi transmission/reception register (8) s i/o counter i (3) synchronous circuit f 1 f 8 f 32 data bus 8 s i/oi interrupt request smi5 lsb msb smi2 smi3 smi3 smi6 smi1 smi0 p9 0/ clk 3 (p9 5/ clk 4 ) p9 2/ s out3 (p9 6/ s out4 ) p9 1/ s in3 (p9 7/ s in4 ) transfer rate register (8) smi6 note: i = 3, 4. ni = a value set in the s i/o transfer rate register i (0363 16 , 0367 16 ). 1/(ni+1) 1/2 2.11.7 s i/o3, 4 s i/o3 and s i/o4 are exclusive clock-synchronous serial i/os. figure 2.11.31 shows the s i/o3, 4 block diagram, and figure 2.11.32 shows the s i/o3, 4 control register.table 2.11.13 shows the specifications of s i/o3, 4. figure 2.11.31 s i/o3, 4 block diagram
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 129 rev. 1.0 M306H2MC-XXXFP si/oi bit rate generator (note 1, note 2) b7 b0 symbol address when reset s3brg 0363 16 indeterminate s4brg 0367 16 indeterminate indeterminate assuming that set value = n, brgi divides the count source by n + 1 00 16 to ff 16 values that can be set w r si/oi transmit/receive register (note) b7 b0 symbol address when reset s3trr 0360 16 indeterminate s4trr 0364 16 indeterminate indeterminate transmission/reception starts by writing data to this register. after transmission/reception finishes, reception data is input. w r s i/oi control register (i = 3, 4) (note 1) symbol address when reset sic 0362 16 , 0366 16 40 16 b7 b6 b5 b4 b3 b2 b1 b0 w r description smi5 smi1 smi0 smi3 smi6 smi7 in ternal synchronous clock select bit transfer direction lect bit s i/oi port select bit (note 2) s out i initial value set bit 0 0 : selecting f 1 0 1 : selecting f 8 1 0 : selecting f 32 1 1 : not to be used b1 b0 0 : external clock 1 : internal clock effective when smi3 = 0 0 : l output 1 : h output 0 : input-output port 1 : s out i output, clk function bit name bit symbol synchronous clock select bit (note 2) 0 : lsb first 1 : msb first smi2 s out i output disable bit 0 : s out i output 1 : s out i output disable (high impedance) note 1: set "1" in bit 2 of the protection register (000a 16 ) in advance to write to the s i/oi control register (i = 3, 4). note 2: when using the port as an input/output port by setting the si/oi port select bit (i = 3, 4) to "1" , be sure to set the sync clock select bit to "1" . nothing is assigned. in an attempt to write to this bit, write 0 . the value, if read, turns out to be 0 . note 1: write a value to this register while transmit/receive halts. note 2: use mov instruction to write to this register. note: write a value to this register while transmit/receive halts. figure 2.11.32 s i/o3, 4 related register
130 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP table 2.11.13 specifications of s i/o3, 4 note 1: n is a value from 00 16 through ff 16 set in the s i/oi transfer rate register (i = 3, 4). note 2: with the external clock selected: before data can be written to the si/oi transmit/receive register (addresses 0360 16 , 0364 16 ), the clki pin input must be in the low state. also, before rewriting the si/oi control register (addresses 0362 16 , 0366 16 ) s bit 7 (s out i initial value set bit), make sure the clki pin input is held low. the s i/oi circuit keeps on with the shift operation as long as the synchronous clock is entered in it, so stop the synchronous clock at the instant when it counts to eight. the internal clock, if selected, automatically stops. note 3: if the internal clock is used for the synchronous clock, the transfer clock signal stops at the h state. item transfer data format transfer clock conditions for transmission/ reception start interrupt request generation timing select function precaution specifications transfer data length: 8 bits with the internal clock selected (bit 6 of 0362 16 , 0366 16 = 1 ): f1/2(ni+1), f8/2(ni+1), f32/2(ni+1) (note 1) with the external clock selected (bit 6 of 0362 16 , 0366 16 = 0):input from the clki terminal (note 2) to start transmit/reception, the following requirements must be met: - select the synchronous clock (use bit 6 of 0362 16 , 0366 16 ). select a frequency dividing ratio if the internal clock has been selected (use bits 0 and 1 of 0362 16 , 0366 16 ). - s out i initial value set bit (use bit 7 of 0362 16 , 0366 16 )= 1. - s i/oi port select bit (bit 3 of 0362 16 , 0366 16 ) = 1. - select the transfer direction (use bit 5 of 0362 16 , 0366 16 ) -write transfer data to si/oi transmit/receive register (0360 16 , 0364 16 ) to use s i/oi interrupts, the following requirements must be met: - clear the si/oi interrupt request bit before writing transfer data to the si/oi transmit/receive register (bit 3 of 0049 16 , 0048 16 ) = 0. rising edge of the last transfer clock. (note 3) lsb first or msb first selection whether transmission/reception begins with bit 0 (lsb) or bit 7 (msb) can be selected. function for setting an s out i initial value selection when using an external clock for the transfer clock, the user can choose the s out i pin output level during a non-transfer time. for details on how to set, see figure 2.11.33. unlike uart0 2, si/oi (i = 3, 4) is not divided for transfer register and buffer. therefore, do not write the next transfer data to the si/oi transmit/receive register (addresses 0360 16 , 0364 16 ) during a transfer. when the internal clock is selected for the transfer clock, s out i holds the last data for a 1/2 transfer clock period after it finished transferring and then goes to a high-impedance state. however, if the transfer data is written to the si/oi transmit/receive register (addresses 0360 16 , 0364 16 ) during this time, s out i is placed in the high-impedance state immediately upon writing and the data hold time is thereby reduced.
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 131 rev. 1.0 M306H2MC-XXXFP (1) functions for setting an s out i initial value when using an external clock for the transfer clock, the s out i pin output level during a non-transfer time can be set to the high or the low state. figure 2.11.33 shows the timing chart for setting an s out i initial value and how to set it. figure 2.11.33 timing chart for setting s out i? initial value and how to set it (2) s i/oi operation timing figure 2.11.34 shows the s i/oi operation timing d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 (i= 3, 4) (i= 3, 4) hiz hiz (i= 3, 4) 1.5 cycle (max) si/oi internal clock transfer clock (note 1) signal written to the s i/oi register s i/oi output s out i s i/oi input s in i si/oi interrupt request bit note2 note 1: with the internal clock selected for the transfer clock, the frequency dividing ratio can be selected using bits 0 and 1 of the s i/oi control register. (i=3,4) (no frequency division, 8-division frequency, 32-division frequency.) note 2: with the internal clock selected for the transfer clock, the s out i pin becomes to the high-impedance state after the transfer finishes. note 3: shown above is the case where the s out i (i = 3, 4) port select bit ="1". "h" "l" "h" "l" "h" "l" "h" "l" "h" "l" "1" "0" figure 22.11.34 s i/oi operation timing chart s i/oi port select bit smi3 = 0 s out i initial value select bit smi7 = 1 (s out i: internal h level) s i/oi port select bit smi3 = 0 1 (port select: normal port s out i) s out i terminal = h output signal written to the s i/oi register = l h l (falling edge) s out i terminal = outputting stored data in the s i/oi transmission/ reception register signal written to the s i/oi transmission/reception register s out i (internal) s out i's initial value set bit (smi7) s out i terminal output s i/oi port select bit (smi3) setting the s out i initial value to h port selection (normal port s out i) d0 (i = 3, 4) initial value = h (note) port output d0 (example) with h selected for s out i: note: the set value is output only when the external clock has been selected. when initializing s out i, make sure the clki pin input is held l level. if the internal clock has been selected or if s out output disable has been set, this output goes to the high-impedance state.
132 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP 2.12 a-d converter the a-d converter consists of one 8-bit successive approximation a-d converter circuit with a capacitive coupling amplifier. pins p10 0 to p10 7 , p9 5 , and p9 6 also function as the analog signal input pins. the direction registers of these pins for a-d conversion must therefore be set to input. the vref connect bit (bit 5 at address 03d7 16 ) can be used to isolate the resistance ladder of the a-d converter from the reference voltage input pin (v ref ) when the a-d converter is not used. doing so stops any current flowing into the resistance ladder from v ref , reducing the power dissipation. when using the a-d converter, start a-d conversion only after setting bit 5 of 03d7 16 to connect v ref . the result of a-d conversion is stored in the a-d registers of the selected pins. table 2.12.1 shows the performance of the a-d converter. figure 2.12.1 shows the block diagram of the a-d converter, and figures 2.12.2 and 2.12.3 show the a-d converter-related registers. note 1: does not depend on use of sample and hold function. note 2: without sample and hold function, set the ad frequency to 250kh z min. with the sample and hold function, set the ad frequency to 1mh z min. item performance method of a-d conversion successive approximation (capacitive coupling amplifier) analog input voltage (note 1) 0v to av cc (v cc ) operating clock ad (note 2) f ad /divide-by-2 of f ad /divide-by-4 of f ad , f ad =f(x in ) resolution8-bit absolute precision without sample and hold function 3lsb with sample and hold function 2lsb operating modes one-shot mode, repeat mode, single sweep mode, repeat sweep mode 0, and repeat sweep mode 1 analog input pins 8 pins (an 0 to an 7 ) + 2pins (anex0 and anex1) a-d conversion start condition software trigger a-d conversion starts when the a-d conversion start flag changes to 1 external trigger (can be retriggered) a-d conversion starts when the a-d conversion start flag is 1 and the __________ ad trg /p9 7 input changes from h to l conversion speed per pin without sample and hold function 49 ad cycles with sample and hold function 28 ad cycles table 2.12.1 performance of a-d converter
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 133 rev. 1.0 M306H2MC-XXXFP 1 / 2 1 / 2 f a d a - d c o n v e r s i o n r a t e s e l e c t i o n (0 3 c 0 1 6 ) ( 0 3 c 2 1 6 ) ( 0 3 c 4 1 6 ) ( 0 3 c 6 1 6 ) ( 0 3 c 8 1 6 ) ( 0 3 c a 1 6 ) ( 0 3 c c 1 6 ) ( 0 3 c e 1 6 ) c k s 1 = 1 c k s 0 = 0 0 0 : n o r m a l o p e r a t i o n 0 1 : a n e x 0 1 0 : a n e x 1 1 1 : e x t e r n a l o p - a m p m o d e a - d r e g i s t e r 0 ( 8 ) a - d r e g i s t e r 1 ( 8 ) a - d r e g i s t e r 2 ( 8 ) a - d r e g i s t e r 3 ( 8 ) a - d r e g i s t e r 4 ( 8 ) a - d r e g i s t e r 5 ( 8 ) a - d r e g i s t e r 6 ( 8 ) a - d r e g i s t e r 7 ( 8 ) r e s i s t o r l a d d e r a n e x 1 a n e x 0 s u c c e s s i v e c o n v e r s i o n r e g i s t e r o p a 1 , o p a 0 = 0 , 1 o p a 0 = 1 o p a 1 = 1 o p a 1 , o p a 0 = 1 , 1 a n 0 a n 1 a n 2 a n 3 a n 5 a n 6 a n 7 a - d c o n t r o l r e g i s t e r 0 ( a d d r e s s 0 3 d 6 1 6 ) a - d c o n t r o l r e g i s t e r 1 ( a d d r e s s 0 3 d 7 1 6 ) v r e f v i n d a t a b u s v r e f a n 4 o p a 1 , o p a 0 = 0 , 0 v c u t = 0 a v s s v c u t = 1 c k s 0 = 1 c k s 1 = 0 c h 2 , c h 1 , c h 0 = 0 0 0 c h 2 , c h 1 , c h 0 = 0 0 1 c h 2 , c h 1 , c h 0 = 0 1 0 c h 2 , c h 1 , c h 0 = 0 1 1 c h 2 , c h 1 , c h 0 = 1 0 0 c h 2 , c h 1 , c h 0 = 1 0 1 c h 2 , c h 1 , c h 0 = 1 1 0 c h 2 , c h 1 , c h 0 = 1 1 1 d e c o d e r c o m p a r a t o r o p a 1 , o p a 0 a d d r e s s e s a d figure 2.12.1 block diagram of a-d converter
134 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP a-d control register 0 (note 1) symbol address when reset adcon0 03d6 16 00000xxx 2 b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit 0 0 0 : an 0 is selected 0 0 1 : an 1 is selected 0 1 0 : an 2 is selected 0 1 1 : an 3 is selected 1 0 0 : an 4 is selected 1 0 1 : an 5 is selected 1 1 0 : an 6 is selected 1 1 1 : an 7 is selected (note 2) ch0 bit symbol bit name function ch1 ch2 a-d operation mode select bit 0 0 0 : one-shot mode 0 1 : repeat mode 1 0 : single sweep mode 1 1 : repeat sweep mode 0 repeat sweep mode 1 (note 2) md0 md1 trigger select bit 0 : software trigger 1 : ad trg trigger trg adst a-d conversion start flag 0 : a-d conversion disabled 1 : a-d conversion started frequency select bit 0 0 : f ad /4 is selected 1 : f ad /2 is selected cks0 w r a-d control register 1 (note) symbol address when reset adcon1 03d7 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a-d sweep pin select bit scan0 scan1 md2 reserved bit must always be set to "0" vcut opa0 vref connect bit opa1 a-d operation mode select bit 1 0 : any mode other than repeat sweep mode 1 1 : repeat sweep mode 1 0 : vref not connected 1 : vref connected external op-amp connection mode bit w r b2 b1 b0 b4 b3 when single sweep and repeat sweep mode 0 are selected 0 0 : an 0 , an 1 (2 pins) 0 1 : an 0 to an 3 (4 pins) 1 0 : an 0 to an 5 (6 pins) 1 1 : an 0 to an 7 (8 pins) b1 b0 when repeat sweep mode 1 is selected 0 0 : an 0 (1 pin) 0 1 : an 0 , an 1 (2 pins) 1 0 : an 0 to an 2 (3 pins) 1 1 : an 0 to an 3 (4 pins) b1 b0 0 0 : anex0 and anex1 are not used 0 1 : anex0 input is a-d converted 1 0 : anex1 input is a-d converted 1 1 : external op-amp connection mode b7 b6 note 1: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. note 2: when changing a-d operation mode, set analog input pin again. frequency select bit 1 0 : f ad /2 or f ad /4 is selected 1 : f ad is selected cks1 note: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. aa a aa a aa a aa aa a a aa a aa aa a a aa a aa a aa a aa aa a a aa a aa a aa a aa a aa a a a aa aa / figure 2.12.2 a-d converter-related registers (1)
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 135 rev. 1.0 M306H2MC-XXXFP figure 2.12.3 a-d converter-related registers (2) a-d control register 2 (note) symbol address when reset adcon2 03d4 16 0000xxx0 2 b7 b6 b5 b4 b3 b2 b1 b0 a-d conversion method select bit 0 : wit h out sam p le an d h ol d 1 : with sample and hold bit symbol bit name function rw note: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. nothing is assigned. in an attempt to write to these bits, write 0 . the value , i f read , turns out t o be 0. symbol address when reset adi(i=0 to 7) indeterminate a-d register i b7 b0 eight bits of a-d conversion result function rw smp reserved bit always set to 0 000 03c0 16 ,03c2 16 ,03c4 16 ,03c6 16 , 03c8 16 ,03ca 16 ,03cc 16 ,03ce 16
136 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP figure 2.12.4 a-d conversion register in one-shot mode (1) one-shot mode in one-shot mode, the pin selected using the analog input pin select bit is used for one-shot a-d conversion. table 2.12.2 shows the specifications of one-shot mode. figure 2.12.4 shows the a-d control register in one-shot mode. table 2.12.2 one-shot mode specifications item specification function the pin selected by the analog input pin select bit is used for one a-d conversion start condition writing 1 to a-d conversion start flag stop condition ? end of a-d conversion (a-d conversion start flag changes to 0, except when external trigger is selected) ? writing 0 to a-d conversion start flag interrupt request generation timing end of a-d conversion input pin one of an 0 to an 7 , as selected reading of result of a-d converter read a-d register corresponding to selected pin a-d control register 0 (note 1) symbol address when reset adcon0 03d6 16 00000xxx 2 b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit bit symbol bit name function ch1 ch2 a-d operation mode select bit 0 md0 md1 trigger select bit 0 : software trigger 1 : ad trg trigger trg adst a-d conversion start flag 0 : a-d conversion disabled 1 : a-d conversion started frequency select bit 0 0: f ad /4 is selected 1: f ad /2 is selected cks0 w r 0 0 a-d control register 1 (note) symbol address when reset adcon1 03d7 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a-d sweep pin select bit scan0 scan1 md2 reserved bit must always be set to "0". vcut opa0 vref connect bit opa1 a-d operation mode select bit 1 0 : any mode other than repeat sweep mode 1 1 : vref connected external op-amp connection mode bit 0 0 : anex0 and anex1 are not used 0 1 : anex0 input is a-d converted 1 0 : anex1 input is a-d converted 1 1 : external op-amp connection mode w r invalid in one-shot mode 0 0 0 0 : an 0 is selected 0 0 1 : an 1 is selected 0 1 0 : an 2 is selected 0 1 1 : an 3 is selected 1 0 0 : an 4 is selected 1 0 1 : an 5 is selected 1 1 0 : an 6 is selected 1 1 1 : an 7 is selected (note 2) b2 b1 b0 0 0 : one-shot mode (note 2) b4 b3 ch0 b7 b6 1 note 1: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. note 2: when changing a-d operation mode, set analog input pin again. frequency select bit1 0 : f ad /2 or f ad /4 is selected 1 : f ad is selected cks1 note: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a /
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 137 rev. 1.0 M306H2MC-XXXFP (2) repeat mode in repeat mode, the pin selected using the analog input pin select bit is used for repeated a-d conver- sion. table 2.12.3 shows the specifications of repeat mode. figure 2.12.5 shows the a-d control register in repeat mode. table 2.12.3 repeat mode specifications item specification function the pin selected by the analog input pin select bit is used for repeated a-d conversion star condition writing 1 to a-d conversion start flag stop condition writing 0 to a-d conversion start flag interrupt request generation timing none generated input pin one of an 0 to an 7 , as selected reading of result of a-d converter read a-d register corresponding to selected pin figure 2.12.5 a-d conversion register in repeat mode a-d control register 0 (note 1) symbol address when reset adcon0 03d6 16 00000xxx 2 b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit ch0 bit symbol bit name function ch1 ch2 a-d operation mode select bit 0 md0 md1 trigger select bit 0 : software trigger 1 : ad trg trigger trg adst a-d conversion start flag 0 : a-d conversion disabled 1 : a-d conversion started frequency select bit 0 0 : f ad /4 is selected 1 : f ad /2 is selected cks0 w r a-d control register 1 (note) symbol address when reset adcon1 03d7 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a-d sweep pin select bit scan0 scan1 md2 vcut opa0 vref connect bit opa1 a-d operation mode select bit 1 1 : vref connected external op-amp connection mode bit w r 01 invalid in repeat mode 0 0 0 0 : an 0 is selected 0 0 1 : an 1 is selected 0 1 0 : an 2 is selected 0 1 1 : an 3 is selected 1 0 0 : an 4 is selected 1 0 1 : an 5 is selected 1 1 0 : an 6 is selected 1 1 1 : an 7 is selected (note 2) b2 b1 b0 0 1 : repeat mode (note 2) b4 b3 0 0 : anex0 and anex1 are not used 0 1 : anex0 input is a-d converted 1 0 : anex1 input is a-d converted 1 1 : external op-amp connection mode b7 b6 1 note 1: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. note 2: when changing a-d operation mode, set analog input pin again. frequency select bit 1 0 : f ad /2 or f ad /4 is selected 1 : f ad is selected cks1 0 : any mode other than repeat sweep mode 1 note: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. a aa a aa a aa a aa a aa a aa a aa a aa a aa a aa a aa a aa a aa a aa a aa a aa #"!4& '#(,(9#&#j/j. /
138 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP (3) single sweep mode in single sweep mode, the pins selected using the a-d sweep pin select bit are used for one-by-one a-d conversion. table 2.12.4 shows the specifications of single sweep mode. figure 2.12.6 shows the a-d control register in single sweep mode. table 2.12.4 single sweep mode specifications figure 2.12.6 a-d conversion register in single sweep mode item specification function the pins selected by the a-d sweep pin select bit are used for one-by-one a-d conversion start condition writing 1 to a-d converter start flag stop condition ? end of a-d conversion (a-d conversion start flag changes to 0, except when external trigger is selected) ? writing 0 to a-d conversion start flag interrupt request generation timing end of a-d conversion input pin an 0 and an 1 (2 pins), an 0 to an 3 (4 pins), an 0 to an 5 (6 pins), or an 0 to an 7 (8 pins) reading of result of a-d converter read a-d register corresponding to selected pin a-d control register 0 (note) symbol address when reset adcon0 03d6 16 00000xxx 2 b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit ch0 bit symbol bit name function ch1 ch2 a-d operation mode select bit 0 1 0 : single sweep mode md0 md1 trigger select bit 0 : software trigger 1 : ad trg trigger trg adst a-d conversion start flag 0 : a-d conversion disabled 1 : a-d conversion started fbequency select bit 0 0 : f ad /4 is selected 1 : f ad /2 is selected cks0 w r a-d control register 1 (note 1) symbol address when reset adcon1 03d7 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a-d sweep pin select bit scan0 scan1 md2 reserved bit m ust always be set to "0". vcut opa0 vref connect bit 0 : an y mode other than repeat sweep mode 1 opa1 a-d operation mode select bit 1 1 : vref connected external op-amp connection mode bit (note 2) w r 1 0 invalid in single sweep mode 0 note 1: i f the a-d control re g ister is rewritten durin g a-d conversion, the conversion resul t isindeterminate. note 2: neither "01" nor "10" can be selected with the external op-amp connection mode bit . b4 b3 when sin g le sweep and repeat sweep mode 0 are selected 0 0 : an 0 , an 1 (2 pins) 0 1 : an 0 to an 3 (4 pins) 1 0 : an 0 to an 5 (6 pins) 1 1 : an 0 to an 7 (8 pins) b1 b0 0 0 : anex0 and anex1 are not used 0 1 : anex0 input is a-d converted 1 0 : anex1 input is a-d converted 1 1 : external op-amp connection mode b7 b6 1 note: i f the a-d control re g ister is rewritten durin g a-d conversion, the conversion result is indeterminate. frequency select bit 1 0 : f ad /2 or f ad /4 is selected 1 : f ad is selected cks1 0
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 139 rev. 1.0 M306H2MC-XXXFP figure 2.12.7 a-d conversion register in repeat sweep mode 0 item specification function the pins selected by the a-d sweep pin select bit are used for repeat sweep a-d conversion start condition writing ??to a-d conversion start flag stop condition writing ??to a-d conversion start flag interrupt request generation timing none generated input pin an 0 and an 1 (2 pins), an 0 to an 3 (4 pins), an 0 to an 5 (6 pins), or an 0 to an 7 (8 pins) reading of result of a-d converter read a-d register corresponding to selected pin (at any time) table 2.12.5 repeat sweep mode 0 specifications (4) repeat sweep mode 0 in repeat sweep mode 0, the pins selected using the a-d sweep pin select bit are used for repeat sweep a-d conversion. table 2.12.5 shows the specifications of repeat sweep mode 0. figure 2.12.7 shows the a-d control register in repeat sweep mode 0. a - d c o n t r o l r e g i s t e r 0 ( n o t e ) s y m b o l a d d r e s s w h e n r e s e t a d c o n 0 0 3 d 6 1 6 0 0 0 0 0 x x x 2 b 7b 6b 5b 4b 3b 2b 1b 0 analog input pin select bit c h 0 b i t s y m b o lb i t n a m e function c h 1 c h 2 a-d operation mode select bit 0 1 1 : repeat sweep mode 0 m d 0 m d 1 trigger select bit 0 : software trigger 1 : ad trg trigger t r g a d s t a-d conversion start flag 0 : a-d conversion disabled 1 : a-d conversion started frequency select bit 0 0 : f ad /4 is selected 1 : f ad /2 is selected cks0 w r a-d control register 1 (note 1) symbol address when reset adcon1 03d7 16 00 16 bit name f unction bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a-d sweep pin select bit scan0 scan1 m d 2 vcut opa0 vref connect bit 0 : any mode other than repeat sweep mode 1 opa1 a-d operation mode select bit 1 1 : vref connected external op-amp connection mode bit (note 2) w r 1 1 invalid in repeat sweep mode 0 0 note 1: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. note 2: neither ?1?nor 10?can be selected with the external op-amp connection mode bit. b4 b3 when single sweep and repeat sweep mode 0 are selected 0 0 : an 0 , an 1 (2 pins) 0 1 : an 0 to an 3 (4 pins) 1 0 : an 0 to an 5 (6 pins) 1 1 : an 0 to an 7 (8 pins) b1 b0 0 0 : anex0 and anex1 are not used 0 1 : anex0 input is a-d converted 1 0 : anex1 input is a-d converted 1 1 : external op-amp connection mode b7 b6 1 note: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. f r e q u e n c y s e l e c t b i t 1 0 : f ad /2 or f ad /4 is selected 1 : f ad is selected c k s 1 r e s e r v e d b it must always be set to "0" . 0
140 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP figure 2.12.8 a-d conversion register in repeat sweep mode 1 (5) repeat sweep mode 1 in repeat sweep mode 1, all pins are used for a-d conversion with emphasis on the pin or pins se- lected using the a-d sweep pin select bit. table 2.12.6 shows the specifications of repeat sweep mode 1. figure 2.12.8 shows the a-d control register in repeat sweep mode 1. table 2.12.6 repeat sweep mode 1 specifications item specification function all pins perform repeat sweep a-d conversion, with emphasis on the pin or pins selected by the a-d sweep pin select bit example : an 0 selected an 0 an 1 an 0 an 2 an 0 an 3 , etc start condition writing 1 to a-d conversion start flag stop condition writing 0 to a-d conversion start flag interrupt request generation timing none generated input pin an 0 (1 pin), an 0 and an 1 (2 pins), an 0 to an 2 (3 pins), an 0 to an 3 (4 pins) reading of result of a-d converter read a-d register corresponding to selected pin (at any time) a-d control register 0 (note) symbol address when reset adcon0 03d6 16 00000xxx 2 b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit ch0 bit symbol bit name f unction ch1 ch2 a-d operation mode select bit 0 1 1 : repeat sweep mode 1 md0 md1 trigger select bit 0 : software trigger 1 : ad trg trigger trg adst a-d conversion start flag 0 : a-d conversion disabled 1 : a-d conversion started frequency select bit 0 0 : f ad /4 is selected 1 : f ad /2 is selected cks0 w r a-d control register 1 (note 1) symbol address when reset adcon1 03d7 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a-d sweep pin select bit scan0 scan1 md2 vcut opa0 vref connect bit 1 : repeat sweep mode 1 opa1 a-d operation mode select bit 1 1 : vref connected external op-amp connection mode bit (note 2) w r 1 1 invalid in repeat sweep mode 1 1 note 1: i f the a-d control re g ister is rewritten durin g a-d conversion, the conversion resul t is indeterminate. note 2: neither "01" nor "10" can be selected with the external op-amp connection mode bit. b4 b3 when repeat sweep mode 1 is selected 0 0 : an 0 (1 pin) 0 1 : an 0 , an 1 (2 pins) 1 0 : an 0 to an 2 (3 pins) 1 1 : an 0 to an 3 (4 pins) b1 b0 0 0 : anex0 and anex1 are not used 0 1 : anex0 input is a-d converted 1 0 : anex1 input is a-d converted 1 1 : external op-amp connection mode b7 b6 1 note: if the a-d control re g ister is rewritten durin g a-d conversion, the conversion result i s indeterminate. frequency select bit 1 0 : f ad /2 or f ad /4 is selected 1 : f ad is selected cks1 reserved bit m ust always be set to "0". 0
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 141 rev. 1.0 M306H2MC-XXXFP analog input external o p -am p an 0 an 7 an 1 an 2 an 3 an 4 an 5 an 6 anex1 anex0 resistor ladder successive conversion register comparator figure 2.12.9 example of external op-amp connection mode (a) sample and hold sample and hold is selected by setting bit 0 of the a-d control register 2 (address 03d4 16 ) to 1. when sample and hold is selected, the rate of conversion of each pin increases. as a result, a 28 f ad cycle is achieved. sample and hold can be selected in all modes. however, in all modes, be sure to specify before starting a-d conversion whether sample and hold is to be used. (b) extended analog input pins in one-shot mode and repeat mode, the input via the extended analog input pins anex0 and anex1 can also be converted from analog to digital. when bit 6 of the a-d control register 1 (address 03d7 16 ) is 1 and bit 7 is 0, input via anex0 is converted from analog to digital. the result of conversion is stored in a-d register 0. when bit 6 of the a-d control register 1 (address 03d7 16 ) is 0 and bit 7 is 1, input via anex1 is converted from analog to digital. the result of conversion is stored in a-d register 1. (c) external operation amp connection mode in this mode, multiple external analog inputs via the extended analog input pins, anex0 and anex1, can be amplified together by just one operation amp and used as the input for a-d conversion. when bit 6 of the a-d control register 1 (address 03d7 16 ) is 1 and bit 7 is 1, input via an 0 to an 7 is output from anex0. the input from anex1 is converted from analog to digital and the result stored in the corresponding a-d register. the speed of a-d conversion depends on the response of the external operation amp. do not connect the anex0 and anex1 pins directly. figure 2.12.9 is an example of how to connect the pins in external operation amp mode.
142 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP 2.13 d-a converter this is an 8-bit, r-2r type d-a converter. the microcomputer contains two independent d-a converters of this type. d-a conversion is performed when a value is written to the corresponding d-a register. bits 0 and 1 (d-a output enable bits) of the d-a control register decide if the result of conversion is to be output. do not set the target port to output mode if d-a conversion is to be performed. output analog voltage (v) is determined by a set value (n : decimal) in the d-a register. v = v ref x n/ 256 (n = 0 to 255) v ref : reference voltage table 2.13.1 lists the performance of the d-a converter. figure 2.13.1 shows the block diagram of the d-a converter. figure 2.13.2 shows the d-a control register. figure 2.13.3 shows the d-a converter equivalent circuit. aaa aaa p9 3 /da 0 aaa p9 4 /da 1 data bus low-order bits d-a register0 (8) r-2r resistor ladder d-a0 output enable bit d-a register1 (8) r-2r resistor ladder d-a1 output enable bit (address 03d8 16 ) (address 03da 16 ) figure 2.13.1 block diagram of d-a converter item performance conversion method r-2r method resolution 8 bits analog output pin 2 channels table 2.13.1 performance of d-a converter
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 143 rev. 1.0 M306H2MC-XXXFP figure 2.13.2 d-a control register d-a control register symbol address when reset dacon 03dc 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 d-a0 output enable bit da0e bit symbol bit name function r w 0 : output disabled 1 : output enabled d-a1 output enable bit 0 : output disabled 1 : output enabled da1e nothing is assigned. in an attempt to write to these bits, write ?? the value, if read, turns out to be ? d-a register symbol address when reset dai (i = 0,1) 03d8 16 , 03da 16 indeterminate w r b7 b0 function r w output value of d-a conversion aa a aa a aa aa a a v ref av ss 2r r 2r r 2r r 2r r 2r r 2r r 2r r 2r 2r da0 msb lsb d-a0 output enable bit "0" "1" d-a0 register0 note 1: the above diagram shows an instance in which the d-a register is assigned 2a 16 . note 2: the same circuit as this is also used for d-a1. note 3: to reduce the current consumption when the d-a converter is not used, set the d-a output enable bit to 0 and set the d- a register to 00 16 so that no current flows in the resistors rs and 2rs. figure 2.13.3 d-a converter equivalent circuit
144 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP 2.14 crc calculation circuit the cyclic redundancy check (crc) calculation circuit detects an error in data blocks. the microcom- puter uses a generator polynomial of crc_ccitt (x 16 + x 12 + x 5 + 1) to generate crc code. the crc code is a 16-bit code generated for a block of a given data length in multiples of 8 bits. the crc code is set in a crc data register each time one byte of data is transferred to a crc input register after writing an initial value into the crc data register. generation of crc code for one byte of data is completed in two machine cycles. figure 2.14.1 shows the block diagram of the crc circuit. figure 2.14.2 shows the crc-related regis- ters. figure 2.14.3 shows the calculation example using the crc calculation circuit figure 2.14.2 crc-related registers symbol address when reset crcd 03bd 16 , 03bc 16 indeterminate b7 b0 b7 b0 (b15) (b8) crc data register w r crc calculation result output register function values that can be set 0000 16 to ffff 16 symbo address when reset crcin 03be 16 indeterminate b7 b0 crc input register w r data input register function values that can be set 00 16 to ff 16 aa a aa a eight low-order bits eight high-order bits data bus high-order bits data bus low-order bits crc data register (16) crc input register (8) crc code generating circuit x 16 + x 12 + x 5 + 1 (addresses 03bd 16 , 03bc 16 ) (address 03be 16 ) figure 2.14.1 block diagram of crc circuit
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 145 rev. 1.0 M306H2MC-XXXFP b15 b0 (1) setting 0000 16 crc data register crcd [03bd 16 , 03bc 16 ] b0 b7 b15 b0 (2) setting 01 16 crc input register crcin [03be 16 ] 2 cycles after crc calculation is complete crc data register crcd [03bd 16 , 03bc 16 ] 1189 16 stores crc code b0 b7 b15 b0 (3) setting 23 16 crc input register crcin [03be 16 ] after crc calculation is complete crc data register crcd [03bd 16 , 03bc 16 ] 0a41 16 stores crc code the code resulting from sending 01 16 in lsb first mode is (1000 0000). thus the crc code in the generating polynomial, (x 16 + x 12 + x 5 + 1), becomes the remainder resulting from dividing (1000 0000) x 16 by (1 0001 0000 0010 0001) in conformity with the modulo-2 operation. thus the crc code becomes (1001 0001 1000 1000). since the operation is in lsb first mode, the (1001 0001 1000 1000) corresponds to 1189 16 in hexadecimal notation. if the crc operation in msb first mode is necessary in the crc operation circuit built in the m16c, switch between the lsb side and the msb side of the input-holding bits, and carry out the crc operation. also switch between the msb and lsb of the result as stored in crc data. 1 0001 0000 0010 0001 1000 0000 0000 0000 0000 0000 1000 1000 0001 0000 1 1000 0001 0000 1000 0 1000 1000 0001 0000 1 1001 0001 1000 1000 1000 1000 lsb msb lsb msb 98 1 1 modulo-2 operation is operation that complies with the law given below. 0 + 0 = 0 0 + 1 = 1 1 + 0 = 1 1 + 1 = 0 -1 = 1 figure 2.14.3 calculation example using the crc calculation circuit
146 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP 2.15 expansion function 2.15.1 expansion function description expansion function cousists of data acquisition function and humming decoder function. each function is controld by expansion memories. (1) data acquisition function corresponds to hardware : teletext, pdc, vps, vbi and epg-j software : xds, wss and vbi-id (2) humming decoder function 8/4 humming and 24/18 humming figure 2.15.1 block diagram of expansion function f s c i n s y n c i n c v i n 1 v e r t i c a l s y n c - s e p a r a t e c i r c u i t c l o c k g e n e r a t o r d a t a s l i c e r c i r c u i t v e r t i c a l s y n c - s e p a r a t e c i r c u i t c l o c k g e n e r a t o r t i m i n g g e n e r a t o r s l i c e r a m 8 / 4 h u m m i n g 2 4 / 1 8 h u m m i n g e x p a n s i o n r e g i s t e r a r b i t r a t e c i r c u i t p 1 1 / s l i c e o n d a t a b u s ( 1 6 b i t ) c p u b l o c k p o r t c o n t r o l c i r c u i t s e r i a l / p a r a r e l l c o n v e r s i o n c i r c u i t c l o c k g e n e r a t o r
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 147 rev. 1.0 M306H2MC-XXXFP 2.15.2 expansion memory expansion function memory is divided by 2 patterns ; slice ram and expansion register. (humming decoder operates by the register placed on sfr). data writing and read out to the slice ram and the expansion register are carried out 16 bit unit by the data setting register (addresses 020e 16 , 0210 16 , 0216 16 and 0218 16 ) placed on sfr. contents of each memory and data setting register are shown in table 2.15.1. table 2.15.1 expansion memory composition expansion memory contents data setting register slice ram store acquisition data. slice ram address control register (020e 16 ) slice ram data control register (0210 16 ) expansion register this register controls data acquisition expansion register address control register (0216 16 ) expansion register data control register (0218 16 )
148 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP 2.15.3 slice ram store 18-line slice data. there are 3 types of slice data : pdc, vps and vbi. all data are stored to addresses which corresponds to acquisition line (ex. 22 line' data is stored to addresses 200 16 to 217 16 ). 24 addresses (sr00x to sr17x) are prepared for 1 line, acquisition data is stored in order from lsb side. then, acquisition datas and field information are stored to the top address of each line. slice ram composite is shown in table 2.15.2. table 2.15.2 slice ram composition for accessing to slice ram data, set accessing address (sa9 to sa0) (shown in table 2.15.2) to slice ram address control register (address 020e 16 ). then read out data from slice ram data control register (address 0210 16 ). when end the data reading, slice ram address control register increments address automatically. then, next address data reading is possible. do not access to unused area of each character codes. must set address to each line because unused area has no address' automatically increment. slice ram bit composition is shown in figure 2.15.2, slice ram access registers are shown in figure 2.15.3 and slice ram access block diagram is shown in figure 2.15.4. sr00f sr17f sr00e sr17e sr00d sr17d sr00c sr17c sr00b sr17b sr00a sr17a sr009 sr179 sr008 sr178 sr007 sr177 sr006 sr176 sr005 sr175 sr004 sr174 sr003 sr173 sr002 sr172 sr001 sr171 sr000 sr170 slice ram addresses (sa9 to sa0) 000 16 001 16 016 16 017 16 remarks ... 018 16 01f 16 ... 020 16 037 16 ... 040 16 1f7 16 ... 200 16 217 16 ... 220 16 237 16 ... 6th line or 318th line slice data sd15 sd14 sd13 sd12 sd11 sd10 sd9 sd8 sd7 sd6 sd5 sd4 sd3 sd2 sd1 sd0 sr00f sr01f sr16f sr17f sr00e sr01e sr16e sr17e sr00d sr01d sr16d sr17d sr00c sr01c sr16c sr17c sr00b sr01b sr16b sr17b sr00a sr01a sr16a sr17a sr009 sr019 sr169 sr179 sr008 sr018 sr168 sr178 sr007 sr017 sr167 sr177 sr006 sr016 sr166 sr176 sr005 sr015 sr165 sr175 sr004 sr014 sr164 sr174 sr003 sr013 sr163 sr173 sr002 sr012 sr162 sr172 sr001 sr011 sr161 sr171 sr000 sr010 sr160 sr170 unused area sr00f sr17f sr00e sr17e sr00d sr17d sr00c sr17c sr00b sr17b sr00a sr17a sr009 sr179 sr008 sr178 sr007 sr177 sr006 sr176 sr005 sr175 sr004 sr174 sr003 sr173 ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... sr002 sr172 sr001 sr171 sr000 sr170 sr00f sr17f sr00e sr17e sr00d sr17d sr00c sr17c sr00b sr17b sr00a sr17a sr009 sr179 sr008 sr178 sr007 sr177 sr006 sr176 sr005 sr175 sr004 sr174 sr003 sr173 ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... sr002 sr172 sr001 sr171 sr000 sr170 ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... 7th line or 319th line slice data 8th line to 21th line or 320th line to 333 line slice data 22th line or 334th line slice data 23th line or 335th line slice data ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ...
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 149 rev. 1.0 M306H2MC-XXXFP figure 2.15.2 slice ram bit composition (2) vps in case of the vps data, 8 bits (a data) are stored for an address from the lsb side. low-order 8 bits stores the acquisition data. and, high-order 8 bits become warning bit, when the send data is not recognized a s bi-phase type. the case of bi-phase data ="1,0" or "0,1" (the bi-phase type) becomes "0" for this warning bit, and it becomes "1" in bi-phase data ="0,0" or "1,1" (it is not the bi-phase type). (for example, bi-phase data of sr011 is "0,0" or "1,1", "1" is set to sr019.) (1) pdc in case of the pdc data, 16 bits (2 data) are stored for the 1 address from the lsb side. pdc vps vbi other sr00f to sr004 0 0 0 0 sr003 field * (note) field * (note) field * (note) 0 sr002 0 0 1 0 sr001 0 1 0 0 sr000 1 0 0 0 s r 0 1 0 s r 0 1 f s r 0 2 0 s 0 2 f s r 0 3 0 s 0 3 f s r 1 4 0 s 1 4 f s r 1 5 0 s 1 5 f l s b m s b l s b m s b l s b m s b s r 1 6 x t o s r 1 7 x a r e u n u s e d a r e a . c l o c k r u n - i n + f l a m i n g c o d e d a t a 1 d a t a 2 d a t a 3 d a t a 4 d a t a 5 d a t a 6 d a t a 4 0 d a t a 3 9 d a t a 4 2 d a t a 4 1 note : * the first field : 1 the second field : 0 s r 0 1 0 s r 0 1 7 s r 0 2 0 s r 0 2 7 s r 0 3 0 s r 0 3 7 s r 0 4 0 s r 0 4 7 s r 0 b 0 s r 0 b 7 s r 0 d 0 s r 0 d 7 s r 0 c 0 s r 0 c 7 l s b m s b l s b m s b s r 0 e x t o s r 1 7 x a r e u n u s e d a r e a . c l o c k r u n - i n + f l a m i n g c o d e d a t a 1 d a t a 2 d a t a 3 d a t a 4 d a t a 1 2 d a t a 1 1 d a t a 1 3 (3) vbi s r 0 1 0 s r 0 1 7 s r 0 2 0 s r 0 2 7 s r 0 3 0 s r 0 3 7 s r 0 4 0 s r 0 4 7 s r 0 5 0 s r 0 5 7 l s b m s b l s b m s b s r 0 6 x t o s r 1 7 x a r e u n u s e d a r e a . c l o c k r u n - i n + f l a m i n g c o d e d a t a 1d a t a 2d a t a 3d a t a 4d a t a 5 the each head address of the address is corresponded to acquisition line has stored next acquisition information.
150 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP figure 2.15.3 slice ram access registers figure 2.15.4 slice ram access block diagram s y m b o la d d r e s sw h e n r e s e t s a0 2 0 e 1 6 0 0 0 0 1 6 s l i c e r a m a d d r e s s c o n t r o l r e g i s t e r f u n c t i o n w r s e t t i n g p o s s i b l e v a l u e 0 0 0 1 6 t o 2 3 7 1 6 s p e c i f y a c c e s s i n g s l i c e r a m a d d r e s s n o t h i n g i s a s s i g n e d . i n a n a t t e m p t t o w r i t e t o t h e s e b i t s , w r i t e 0 . t h e v a l u e , i f r e a d , t u r n s o u t t o b e i n d e t e r m i n a t e d . s y m b o la d d r e s sw h e n r e s e t s d0 2 1 0 1 6 0 0 0 0 1 6 s l i c e r a m d a t a c o n t r o l r e g i s t e r f u n c t i o n w r r e a d o u t t h e d a t a o f s l i c e r a m . re a d o u t d a t a o f s l i c e r a m w h i c h i s s p e c i f i e d b y s l i c e r a m a d d r e s s c o n t r o l r e g i s t e r ( a d d r e s s 0 2 0 e 1 6 ) b y r e a d i n g t h i s r e g i s t e r . n o t e : d a t a a c c e s s m u s t b e 1 6 - b i t u n i t . 8 - b i t u n i t a c c e s s i s d i s a b l e . n o t e : w h e n a c c e s s t o s l i c e r a m , m u s t b e s e t s l i c e r a m a t f i r s t , t h e n u s e s l i c e r a m d a t a c o n t r o l r e g i s t e r ( 0 2 1 0 1 6 ) . s l i c e r a m a d d r e s s c o n t r o l r e g i s t e r i n c r e m e n t s b y a c c e s s i n g s l i c e r a m d a t a c o n t r o l r e g i s t e r . s o , i t i s n o t n e c c e s a r y t o s e t t i n g t h e n e x t s l i c e r a m a d d r e s s . b 1 5b 9b 8 b 7 b 0 b 1 5b 9b 8 b 7 b 0 d a t a b u s ( 1 6 - b i t ) ( a d d r e s s 0 2 0 e 1 6 ) ( a d d r e s s 0 2 1 0 1 6 ) s l i c e r a m d a t a c o n t r o l r e g i s t e r ( 1 6 ) ( s d 1 5 t o s d 0 ) s l i c e r a m a d d r e s s c o n t r o l r e g i s t e r ( 1 0 ) ( s a 9 t o s a 0 ) i n c r e m e n t a u t o m a t i c a l l y a f t e r d a t a a c c e s s s l i c e r a m
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 151 rev. 1.0 M306H2MC-XXXFP 2.15.4 expansion register control data acquisition function. expansion register composition is shown in table 2.15.3. da5 to da0 dd15 dd14 dd13 dd12 dd11 dd10 dd9 dd8 dd7 dd6 dd5 dd4 dd3 dd2 dd1 dd0 00 16 01 16 02 16 03 16 04 16 05 16 06 16 07 16 08 16 09 16 0a 16 0b 16 0c 16 0d 16 0e 16 0f 16 10 16 11 16 _ _ _ test2 test1 test0 _ _ _ _ _ _ _ _ _ _ _ ptd8 _ _ _ _ _ _ _ ptc8 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ adon _ _ sel_pdch _ _ _ _ _ _ _ _ _ _ syncsep_on0 __ slslvl sli_vp2 sli_vp1 sli_vp0 _ _ vps_sub _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ remarks _ _ _ test setting _ _ _ _ _ _ _ port setting time base setting display control setting _ slicer control setting sync separation, slice setting _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ stby0 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ timbas _ _ _ _ _ _ _ _ _ _ _ _ _ _ _nxp _ _ _ _ _ _ _ _ _ _ _ _ 12 16 13 16 14 16 15 16 16 16 17 16 18 16 19 16 1a 16 1b 16 1c 16 1d 16 1e 16 1f 16 _ _ _ _ _ _ seki5 seki4 seki3 seki2 seki1 seki0 _ sel_vpsh _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ stby1 _ _ _ vps_vco_on __ pdc_vco_on _ _ xtal_vco _ _ _ _ _ _ _ pd2 pd1 _ pdc_hp10 pdc_hp9 pdc_hp8 pdc_hp7 pdc_hp6 pdc_hp5 pdc_hp4 pdc_hp3 hgsl hgsls _ softsls _ _ _ _ vps_hp10 vps_hp9 vps_hp8 vps_hp7 vps_hp6 vps_hp5 vps_hp4 vps_hp3 _ _ _ vps_line4 vps_line3 vps_line2 vps_line 1 vps_line0 _ _ vbif2 vbif1 vpsf2 vpsf1 pdcf2 pdcf1 vps_flc7 vps_flc6 vps_flc5 vps_flc4 vps_flc3 vps_flc2 vps_flc1 vps_flc0 pdc_flc7 pdc_flc6 pdc_flc 5 pdc_flc4 pdc_flc3 pdc_flc2 pdc_flc1 pdc_flc0 _ _ _ chk_vps _ _ _ _ _ _ chk_pdc _ _ _ _ _ _ selpeek div_pdc8 div_pdc7 div_pdc6 div_pdc5 div_pdc4 div_pdc3 div_pdc2 div_pdc1 div_pdc0 div_pdcs2 div_pdcs1 div_pdcs0 _ _ _ _ div_vps8 div_vps7 div_vps6 div_vps5 div_vps4 div_vps3 div_vps2 div_vps1 div_vps0 div_vpss2 div_vpss1 div_vpss0 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ngsync _ _ fld ____ macro, field flag vps frequency setting pdc frequency setting pdc, vps flaming setting pdc, vps flaming setting acquisition setting vps slice position setting pdc slice position setting oscillation on/off setting _ acquisition setting 20 16 _ _ min5 min4 min3 min2 min1 min0 _ _ max5 max4 max3 max2 max1 max0 21 16 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ acquisition setting 22 16 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ table 2.15.3 expansion register composition
152 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP for accessing to expantion register data, set accessing address (da5 to da0) (shown in table 2.15.3) to expantion register address control register (address 0216 16 ). then write data (dd15 to dd0) by expantion register data control register (address 0218 16 ). when end the data accessing, expantion register address control register increments address automatically. then, next address data writing is possible. expantion register access registers are shown in figure 2.15.5, expansion register access block dia- gram is shown in figure 2.15.6, and expansion register bit compositions are shown in p153 to 163. figure 2.15.5 expansion register access registers composition figure 2.15.6 expansion register access block diagram s y m b o la d d r e s sw h e n r e s e t d a0 2 1 6 1 6 0 0 0 0 1 6 e x p a n s i o n r e g i s t e r a d d r e s s c o n t r o l r e g i s t e r f u n c t i o n w r s e t t i n g p o s s i b l e v a l u e 0 0 1 6 t o 2 2 1 6 s p e c i f y a c c e s s i n g e x p a n s i o n r e g i s t e r a d d r e s s n o t h i n g i s a s s i g n e d . i n a n a t t e m p t t o w r i t e t o t h e s e b i t s , w r i t e 0 . t h e v a l u e , i f r e a d , t u r n s o u t t o b e i n d e t e r m i n a t e d . s y m b o la d d r e s sw h e n r e s e t d d0 2 1 8 1 6 0 0 0 0 1 6 e x p a n s i o n r e g i s t e r d a t a c o n t r o l r e g i s t e r f u n c t i o n w r s e t t i n g p o s s i b l e v a l u e 0 0 0 0 1 6 t o f f f f 1 6 w r i t e a n d r e a d o u t t h e d a t a o f e x p a n s i o n r e g i s t e r w h i c h i s s p e c i f i e d b y e x p a n s i o n r e g i s t e r a d d r e s s c o n t r o l r e g i s t e r ( a d d r e s s 0 2 1 6 1 6 ) n o t e : d a t a a c c e s s m u s t b e 1 6 - b i t u n i t . 8 - b i t u n i t a c c e s s i s d i s a b l e . n o t e 1 : w h e n a c c e s s t o e x p a n s i o n r e g i s t e r , m u s t b e s e t e x p a n s i o n r e g i s t e r a d d r e s s a t f i r s t , t h e n u s e e x p a n s i o n r e g i s t e r d a t a c o n t r o l r e g i s t e r ( 0 2 1 8 1 6 ) . n o t e 2 : w h e n b i t 8 = 0 s e t t i n g , e x p a n s i o n r e g i s t e r d a t a c o n t r o l r e g i s t e r i n c r e m e n t s b y a c c e s s i n g e x p a n s i o n r e g i s t e r d a t a c o n t r o l r e g i s t e r , s o i t i s n o t n e c c e s a r y t o s e t t i n g t h e n e x t e x p a n s i o n r e g i s t e r a d d r e s s . w h e n b i t 8 = 1 s e t t i n g , t h e a d d r e s s i s f i x e d . b 1 5b 8 b 7 b 0 b 5 b 1 5b 8 b 7 b 0 n o t h i n g i s a s s i g n e d . i n a n a t t e m p t t o w r i t e t o t h e s e b i t s , w r i t e 0 . t h e v a l u e , i f r e a d , t u r n s o u t t o b e i n d e t e r m i n a t e d . e x p a n s i o n r e g i s t e r a d d r e s s a u t o i n c r e m e n t s s e t 0 : v a i d / 1 : i n v a i d ( n o t e 2 ) data bus (16-bit) (address 0216 16 ) (address 0218 16 ) expansion register data control register (16) (dd15 to dd0) expansion register address control register (5) (da5 to da0) increment automatically after data access expansion register (da8)
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 153 rev. 1.0 M306H2MC-XXXFP expansion register construction (1) address 00 16 ( = da5 to 0) (2) addresses 01 16, 02 16 ( = da5 to 0) dd15 dd8dd7 dd0 rw bit symbol bit name function 00 0 00 0 0 0 0 00 0 00 0 0 ? must always be set to "0". reserved bit (3) address 03 16 ( = da5 to 0) dd15 dd8dd7 dd0 rw bit symbol bit name function 00 0 0 0 0 00 0 00 0 0 ? must always be set to "0". reserved bit ? test0 test1 test2 test bit must always be set to "0". must always be set to "0". reserved bit stby0 normal mode stand-by mode 0 1 stand-by mode selection bit dd15 dd8dd7 dd0 rw bit symbol bit name function 00 0 00 0 00 00 0 00 0 0 ? must always be set to "0". reserved bit ? must always be set to "0". reserved bit (4) address 04 16 to 0a 16 ( = da5 to 0) dd15 dd8dd7 dd0 rw bit symbol bit name function 00 0 00 0 0 0 0 00 0 00 0 0 ? must always be set to "0". reserved bit
154 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP (5) address 0b 16 ( = da5 to 0) dd15 dd8dd7 dd0 rw bit symbol bit name function 00 00 0 0 0 0 0 0 00 0 0 ptd8 when port output : fixed to "l" when sliceon output : specified negative polarity when port output : fixed to "h" when sliceon output : specified positive polarity 0 1 port p11 data selection bit 1 must always be set to "0". reserved bit 1 must always be set to "0". reserved bit 1 must always be set to "0". reserved bit ptc8 port p11 output selection bit 0 p11 output 1 sliceon output (6) address 0c 16 ( = da5 to 0) dd15 dd8dd7 dd0 rw bit symbol bit name function 00 0 0 0 0 0 0 0 0 0 00 0 0 1 must always be set to "0". reserved bit 1 must always be set to "0". reserved bit timbas time base selection bit 0 time base off 1 time base on (7) address 0d 16 ( = da5 to 0) dd15 dd8dd7 dd0 rw bit symbol bit name function 00 0 0 0 0 0 0 0 0 0 00 0 0 1 must always be set to "0". reserved bit 1 must always be set to "0". reserved bit nxp broadcast method selection bit 0 ntsc 1 pal (8) address 0e 16 ( = da5 to 0) dd15 dd8dd7 dd0 rw bit symbol bit name function 00 0 00 0 0 0 0 00 0 00 0 0 1 must always be set to "0". reserved bit
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 155 rev. 1.0 M306H2MC-XXXFP (9) address 0f 16 ( = da5 to 0) ? ? ? dd15 dd8dd7 dd0 rw bit symbol bit name function reserved bit must always be set to "0". reserved bit must always be set to "0". 00 0000 000000 0 0 sel_pdch adon 0 data acquisition off 1 data acquisition on reserved bit must always be set to "0". data acquisition control bit pdc clock selection bit generats pdc clock in based on fscin pin input signal. do not set 0 1 (10) address 10 16 ( = da5 to 0) ? ? ? ? ?
156 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP (12) address 12 16 ( = da5 to 0) (13) addresses 13 16, 14 16 ( = da5 to 0) ? dd15 dd8dd7 dd0 rw bit symbol bit name function reserved bit must always be set to "0". 00 0 0 000 000 00000 0 dd15 dd8dd7 dd0 rw seki0 seki1 seki2 seki3 seki4 seki5 00 00 0 000 seki1 seki0 n 0 0 1 1 0 1 0 1 5 4 3 2 n times of the digital value after ad is done. seki3 seki2 n 0 0 1 1 0 1 0 1 4 3 1 not differentiate seki5 seki4 n 0 0 1 1 0 1 0 1 4 3 1 not differentiate it is differentiated for digital value after the seki0, 1 operation at digital value in the before n/8 period(clock run-in period). sel_vpsh bit symbol bit name function data acquisition control bit 1 data acquisition control bit 2 data acquisition control bit 3 it is differentiated for digital value after the seki3, 2 operation at digital value in the after n/8 period(clock run-in period). must always be set to "0" reserved bit ? (11) address 11 16 ( = da5 to 0) ? ? ? dd15 dd8dd7 dd0 rw bit symbol bit name function reserved bit must always be set to "0". 00 1 0 000 000 00000 0 reserved bit must always be set to "1". reserved bit must always be set to "0".
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 157 rev. 1.0 M306H2MC-XXXFP (14) address 15 16 ( = da5 to 0) ? ? ? ? ? dd15 dd8dd7 dd0 rw bit symbol bit name function 0 1 0 1 0 1 0 1 must always be set to "0". reserved bit must always be set to "0". reserved bit must always be set to "0". reserved bit must always be set to "0". reserved bit must always be set to "0". reserved bit xtal_vco pdc_vco_on vps_vco_on stby1 synchronizing clock off synchronizing clock oscillation pdc clock off pdc clock oscillation vps and vbi clock off vps and vbi clock oscillation normal mode stand-by mode. 00 00 00 0 0000 0 synchronous clock oscillation selection bit pdc clock oscillation selection bit vps and vbi clock oscillation selection bit stand-by mode selection bit (15) address 16 16 ( = da5 to 0) ? ? reserved bit must always be set to "0". dd15 dd8dd7 dd0 rw bit symbol bit name function pdc_hp3 pdc_hp4 pdc_hp5 pdc_hp6 pdc_hp7 pdc_hp8 pdc_hp9 pdc_hp10 pd1 pd2 adjust clock phase for data slicer. normaly, pd2 to pd1=(10) 2 fixed. pdc acquisition check start position selection bit if the pdc acquisition check start position is pdc_hs, pdc_hs= t3 ? 2 (n-3) pdc_hpn 10 n=3 0 t3 : pdc clock run-in cycle 2 set to flaming code check start position set by the 144ns (1bit) 0 0 pdc, vps, vbi clock phase control bit 0 0 reserved bit must always be set to "0". 0
158 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP (16) address 17 16 ( = da5 to 0) ? ? ? ?? dd15 dd8dd7 dd0 rw bit symbol bit name function vps_hp3 vps_hp4 vps_hp5 vps_hp6 vps_hp7 vps_hp8 vps_hp9 vps_hp10 softsls hgsls hgsl reserved bit must always be set to "0". vps and vbi acquisition check start position selection bit if vps and vbi acquisition check start position is vps_hs, vps_hs= t2 ? 2 (n-3) vps_hpn 10 n=3 100 0 0 t2 : vps or vbi clock run-in cycle 2 set to flaming code check start position set by the 200ns (1bit)....vps set by the 800ns (1bit)....vbi must always be set to "1". data slicer control bit reserved bit must always be set to "0". reserved bit must always be set to "0". nothing is assigned. slicer selection bit data slicer control bit 0 pdc, vps, vbi 1 xds, wss, vbi-id 0 pdc, vps 1 vbi (16) address 17 16 ( = da5 to 0) (17) address 18 16 ( = da5 to 0) dd15 dd8dd7 dd0 rw bit symbol bit name function 00 0 00 0 0 0 0 00 0 00 0 0 ? must always be set to "0". reserved bit
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 159 rev. 1.0 M306H2MC-XXXFP (18) address 19 16 ( = da5 to 0) dd15 dd8dd7 dd0 rw bit symbol bit name function pdcf1 pdcf2 vpsf1 vpsf2 vbif1 vbif2 vpsf_line0 vpsf_line1 vpsf_line2 vpsf_line3 vpsf_line4 0 1 0 1 0 1 0 1 0 1 0 1 00 0 0 0 do not acquisition field 1 pdc data acquisition field 1 pdc data do not acquisition field 2 pdc data acquisition field 2 pdc data do not acquisition field 1 vps data acquisition field 1 vps data do not acquisition field 2 vps data acquisition field 2 vps data do not acquisition field 1 vbi data acquisition field 1 vbi data do not acquisition field 2 vbi data acquisition field 2 vbi data pdc data acquisition selection bit (field1) vbi data acquisition selection bit (field2) vbi data acquisition selection bit (field1) vps data acquisition selection bit (field2) vps data acquisition selection bit (field1) pdc data acquisition selection bit (field2) ? reserved bit must always be set to "0". ? reserved bit must always be set to "0". vps data acquisition line selection bit when vps data acquisition line is vps_lines, vps_lines = 2 n vps_linen + 7 4 n=0 (vps_line4 to vps line0 = " 01001 2 " fixed) setting value from 00000 2 to 10000 2 (7th line to 23 line) fixed to 16th line normally.)
160 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP (19) address 1a 16 ( = da5 to 0) clock run - in flaming code (8 bits) pdc_flc0 to pdc_flc7 data setting clock run - in flaming code (24 bits) data pdc_flc4 to 7 vps_flc0 to 7 crock run - in flaming code (16 bits) data vps_flc0 to vps_flc7 flaming code (16 bits) data vps_flc0 to 3 vps_flc4 to 7 dd15 dd8dd7 dd0 rw bit symbol bit name function pdc_flc0 pdc_flc1 pdc_flc2 pdc_flc3 pdc_flc4 pdc_flc5 pdc_flc6 pdc_flc7 vps_flc0 vps_flc1 vps_flc2 vps_flc3 vps_flc4 vps_flc5 vps_flc6 vps_flc7 flaming code selection bit at pdc acquisition flaming code selection bit at vbi acquisition flaming code selection bit at vps and vbi acquisition [pdc] pdc_flc0 to 7 = 11100100 [vbi] set last 12bits [vps] when vps_sub (address12 16 ) = 0 set last 8bits vps_flc0 to 7 = 10011001 vps_sub = 1 vps_flc0 to 7 = 10001001 (set first 4bits) (set last 4 bits) = 8bits
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 161 rev. 1.0 M306H2MC-XXXFP (20) address 1b 16 ( = da5 to 0) ? ? ? ? ? dd15 dd8dd7 dd0 rw bit symbol bit name function reserved bit must always be set to "0". 00 0 000 0000000 0 reserved bit reserved bit must always be set to "0". must always be set to "0". chk_pdc 5 flaming code check selection bit 0 1 pdc_flc5 valid pdc_flc5 invalid (note1) chk_vps 5 flaming code check selection bit 0 1 vps_flc5 valid vps_flc5 invalid (note1) note1. at vbi acquisition, must be set to "1". (21) address 1c 16 ( = da5 to 0) ?
162 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP (22) address 1d 16 ( = da5 to 0) ? dd15 dd8dd7 dd0 rw bit symbol bit name function div_vpss0 div_vpss1 div_vpss2 div_vps0 div_vps1 div_vps2 div_vps3 div_vps4 div_vps5 div_vps6 div_vps7 div_vps8 pll control bit for vps and vbi pll divided value selection bit for vps and vbi reserved bit must always be set to "0". control the acquisition clock frequency f vps for vps and vbi. div_vps8 to div_vps0 = (000001111) 2 div_vpss2 to div_vpss0 = (110) 2 00 0 0 (23) address 1e 16 ( = da5 to 0) dd15 dd8dd7 dd0 rw bit symbol bit name function 00 0 00 0 0 0 0 00 0 00 0 0 ? must always be set to "0". reserved bit (24) address 1f 16 ( = da5 to 0) ? dd15 dd8dd7 dd0 rw bit symbol bit name function reserved bit reserved bit writing is disable. reading exclusive bit. ? ? ngsync 0 normal 1 abnormalities synchronous signal detected flag (note 1) fld 0 the secound field. 1 the first field. fild flag ? ? reserved bit writing is disable. reading exclusive bit. ? ? ? writing is disable. reading exclusive bit. note 1: this flag detects unwanted signals during the sync signal (slice period).
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 163 rev. 1.0 M306H2MC-XXXFP (25) address 20 16 ( = da5 to 0) dd15 dd8dd7 dd0 rw min0 set acquisition data sampling maximum value after a/d conversion. acquisition data sampling minimum value selection bit max0 acquisition data sampling maximum value selection bit 0 0 00 5 n=0 samax = 2 n ? maxn (note1) 5 n=0 max5 max4 max3 max2 max1 min5 min4 min3 min2 min1 note1. clock run in samax samin video signal sampling image after a/d conversion a/d conversion maximun value a/d conversion minimum value bit symbol bit name function must always be set to "0". reserved bit must always be set to "0". reserved bit set acquisition data sampling minimun value after a/d conversion. samin = 2 n ? minn (note1) (26) address 21 16 , 22 16 ( = da5 to 0) dd15 dd8dd7 dd0 rw bit symbol bit name function 00 0 00 0 0 0 0 00 0 00 0 0 ? must always be set to "0". reserved bit
164 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP 2.15.5 expansion register construction composition (1) acquisition timming the sliceon signal is output in the acquisition possible period. figure 2.15.7 acquisition timing 1 2 3 4 5 6 789 1 9 2 2 2 1 2 0 2 32 4 6 2 26 2 36 2 46 2 5 3 1 43 1 53 1 6 3 1 73 1 8 3 1 9 3 2 0 3 2 13 3 13 3 2 3 1 0 3 1 1 3 1 23 1 3 3 3 3 3 3 43 3 5 3 3 6 t h e f i r s t f i e l d t h e s e c o n d f i e l d v e r t i c a l b l a n k i n g e r a s e p e r i o d p u l s e a c q u i s i t i o n p o s s i b l e p e r i o d s l i c e o n o u t p u t p e r i o d t h e s c a n n i n g l i n e s n u m b e r i n f i g u r e i s c o r r e s p o n d s t o s l i c e r a m .
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 165 rev. 1.0 M306H2MC-XXXFP figure 2.15.8 decoded result 2.15.6 8/4 humming decoder 8/4 humming decoder opetates only by written the data which 8/4 humming- decoded to 8/4 humming register (address 021a 16 ). 8/4 humming register consists of 16 bits, can decode two data at a time. can obtain the decoded result by reading 8/4 humming register, and the decoded value and error information are output. corrects and outputs the decoded value for single error, and outputs only error information for double error. decoded result is shown in figure 2.15.8 and humming 8/4 register com- position is shown in figure 2.15.9. figure 2.15.9 humming 8/4 register composition w r i t i n g a d d r e s s r e a d i n g 8 / 4 h u m m i n g r e g i s t e r h u m m i n g d a t a ? h u m m i n g d a t a ? e r r o r i n f o r m a t i o n ? e r r o r i n f o r m a t i o n ? 0 2 1 a 1 6 0 0 0 0 1 o u t p u t w h e n d o u b l e e r r o r 1 o u t p u t w h e n s i n g l e e r r o r 1 o u t p u t w h e n s i n g l e e r r o r 1 o u t p u t w h e n d o u b l e e r r o r m s b m s b l s b l s b m s b l s b m s b l s b d e c o d e v a l u e ? d e c o d e v a l u e ? b 1 5b 8b 7 b 0 s y m b o la d d r e s sw h e n r e s e t h m 80 2 1 a 1 6 0 0 0 0 1 6 h u m m i n g 8 / 4 r e g i s t e r f u n c t i o n w r 8 / 4 h u m m i n g d e c o d e r o p e t a t e s o n l y b y w r i t t e n t h e d a t a w h i c h 8 / 4 h u m m i n g - d e c o d e d t o 8 / 4 h u m m i n g r e g i s t e r . c a n o b t a i n t h e d e c o d e d r e s u l t b y r e a d i n g t h i s r e g i s t e r , a n d c a n d e c o d e 2 c o u p l e s o f d a t a a t t h e s a m e t i m e .
166 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP 2.15.7 24/18humming decoder 24/18 humming decoder operates only by written the data which 24/18 humming-encoded to 24/18 humming register 0 (address 021c 16 ) and 1 (address 021e 16 ). can obtain the decoded result by reading the same 24/18 humming register. decoded result is shown in figure 2.15.10 and humming 24/18 register composition is shown in figure 2.15.11. figure 2.15.10 decoded result figure 2.15.11 humming 24/18 register composition b 1 5b 8b 7b 0 s y m b o la d d r e s sw h e n r e s e t h m 00 2 1 c 1 6 0 0 0 0 1 6 h u m m i n g 2 4 / 1 8 r e g i s t e r 0 f u n c t i o n w r 2 4 / 1 8 h u m m i n g d e c o d e r o p e t a t e s b y t w o w a y s : w r i t i n g d a t a l o w - o r d e r a n d m i d d l e - o r d e r 1 6 b i t s t o t h i s r e g i s t e r a n d w r i t i n g d a t a h i g h - o r d e r 8 b i t s t o h u m m i n g 2 4 / 1 8 r e g i s t e r 1 ( 0 2 1 e 1 6 ) . c a n o b t a i n t h e d e c o d e d r e s u l t b y r e a d i n g t h i s r e g i s t e r a n d h u m m i n g 2 4 / 1 8 r e g i s t e r 1 . b 1 5b 8b 7b 0 s y m b o la d d r e s sw h e n r e s e t h m 10 2 1 e 1 6 0 0 0 0 1 6 h u m m i n g 2 4 / 1 8 r e g i s t e r 1 f u n c t i o n w r 2 4 / 1 8 h u m m i n g d e c o d e r o p e t a t e s b y t w o w a y s : w r i t i n g d a t a l o w - o r d e r a n d m i d d l e - o r d e r 1 6 b i t s t o h u m m i n g 2 4 / 1 8 r e g i s t e r 0 ( 0 2 1 c 1 6 ) t o t h i s r e g i s t e r a n d w r i t i n g d a t a h i g h - o r d e r 8 b i t s t o t h i s r e g i s t e r . c a n o b t a i n t h e d e c o d e d r e s u l t b y r e a d i n g t h i s r e g i s t e r a n d h u m m i n g 2 4 / 1 8 r e g i s t e r 0 . output after correcting single error w r i t i n g w r i t i n g a d d r e s s a d d r e s s r e a d i n g r e a d i n g h u m m i n g d a t a l d e c o d e v a l u e 2 4 / 1 8 h u m m i n g r e g i s t e r 1 2 4 / 1 8 h u m m i n g r e g i s t e r 0 h u m m i n g d a t a h h u m m i n g d a t a m e r r o r i n f o r m a t i o n d e c o d e v a l u e 0 2 1 e 1 6 0 0 0 0 0 1 o u t p u t w h e n d o u b l e e r r o r 1 o u t p u t w h e n s i n g l e e r r o r l s b m s b m s b l s b 0 0 2 1 c 1 6 0 00 0 00
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 167 rev. 1.0 M306H2MC-XXXFP continuous error correction when uses humming 8/4 (address 021a 16 ) at tha same time as humming 24/18, can do the continu- ous error correction. continuous error correction sequence is shown in figure 2.15.12. figure 2.15.12 continuous error correction sequence then, because using a part of circuit of humming 8/4 about this operation, cannot use this operation at the same time. when using the humming circuit, do the decoded result reading operation at once after the setting data of humming. and do not access other memories (including the humming circuit) before reading of the decoded result. ? humming data ? ml ? humming data ? lh ? humming data ? hm ? humming data ? ml ? humming data ? lh humming data humming data humming data humming data humming data humming data ? humming data ? hm a b c d e f 1. writes data a to address 021c 16 and writes data b to address 021e 16 . (setting the humming data ? and l of humming data ? .) 2. reads addresses 021c 16 and 021e 16 data (obtains the de- coded value and error information on the humming data ? ). 3. writes data c to address 021a 16 (setting h and m of the hum- ming data ? ). 4. reads addresses 021c 16 and 021e 16 data (obtains the de- coded value and error information on the humming data ? ). 5. writes data d to address 021c 16 and writes data e to 021e 16 (setting the humming data ? and l of humming data ? .) 6. reads addresses 021c 16 and 021e 16 data (obtains the de- coded value and error information on the humming data ? ). 7. writes data f to address 021a 16 (setting h and m of the hum- ming data ? ). 8. reads addresses 021c 16 and 021e 16 data (obtains the de- coded value and error information on the humming data ? ).
168 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP figure 2.15.13 pins for expansion memory(1) 2.15.8 i/o composition of pins for expansion memory figure 2.15.13 and figure 2.15.14 show pins for expansion memory. cvin1 cvin1 v cc v ss syncin input v cc v ss from internal circuit v dd2 v ss2 (note 2) (note 2) to slicer p11/sliceon output v cc v ss port p11 output selection bit (note 1) port p11 data selection bit (note 1) v cc v ss note1 : refer expansion register construction note2 : expamsion register construction composition to internal circuit from internal circuit to internal circuit from internal circuit (note 2) do not apply a voltage higher than vcc to each port.
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 169 rev. 1.0 M306H2MC-XXXFP figure 2.15.14 pins for expansion memory(2) f s c i n l p 2 , l p 3 , l p 4 v c c v s s o u t p u t i n p u t v c c v s s s v r e f v c c v s s v d d 2 v s s 2 v d d 2 v s s 2 v s s 2 n o t e 1 : e x p a m s i o n r e g i s t e r c o n s t r u c t i o n c o m p o s i t i o n f r o m i n t e r n a l c i r c u i t ( n o t e 1 ) t o i n t e r n a l c i r c u i t i n p u t ( n o t e 1 ) t o i n t e r n a l c i r c u i t f r o m i n t e r n a l c i r c u i t ( n o t e 1 ) t o i n t e r n a l c i r c u i t f r o m i n t e r n a l c i r c u i t do not apply a voltage higher than vcc to each port.
170 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP 2.16 programmable i/o ports there are 87 programmable i/o ports: p0 to p10 (excluding p8 5 ). each port can be set independently for input or output using the direction register. a pull-up resistance for each block of 4 ports can be set. p8 5 is an input-only port and has no built-in pull-up resistance. figures 2.16.1 to 2.16.4 show the programmable i/o ports. figure 2.16.5 shows the i/o pins. each pin functions as a programmable i/o port and as the i/o for the built-in peripheral devices. to use the pins as the inputs for the built-in peripheral devices, set the direction register of each pin to input mode. when the pins are used as the outputs for the built-in peripheral devices (other than the d-a converter), they function as outputs regardless of the contents of the direction registers. when pins are to be used as the outputs for the d-a converter, do not set the direction registers to output mode. see the descriptions of the respective functions for how to set up the built-in peripheral devices. (1) direction registers figure 2.16.6 shows the direction registers. these registers are used to choose the direction of the programmable i/o ports. each bit in these regis- ters corresponds one for one to each i/o pin. in memory expansion and microprocessor mode, the contents of corresponding direction register of pins ________ ________ _____ ________ ______ ________ ________ ________ __________ __________ a0 to a19, d0 to d15, cs0 to cs3, rd, wrl/wr, wrh/bhe, ale, rdy, hold, hlda and bclk cannot be modified. note: there is no direction register bit for p8 5 . (2) port registers figure 2.16.7 shows the port registers. these registers are used to write and read data for input and output to and from an external device. a port register consists of a port latch to hold output data and a circuit to read the status of a pin. each bit in port registers corresponds one for one to each i/o pin. in memory expansion and microprocessor mode, the contents of corresponding port register of pins a0 to ________ ________ _____ ________ ______ ________ ________ ________ __________ __________ a19, d0 to d15, cs0 to cs3, rd, wrl/wr, wrh/bhe, ale, rdy, hold, hlda and bclk cannot be modified. (3) pull-up control registers figure 2.16.8 shows the pull-up control registers. the pull-up control register can be set to apply a pull-up resistance to each block of 4 ports. when ports are set to have a pull-up resistance, the pull-up resistance is connected only when the direction register is set for input. however, in memory expansion mode and microprocessor mode, the pull-up control register of p0 to p3, p40 to p43, and p5 is invalid. the contents of register can be changed, but the pull-up resistance is not connected. (4) port control register figure 2.16.9 shows the port control register. the bit 0 of port control resister is used to read port p1 as follows: 0 : when port p1 is input port, port input level is read. when port p1 is output port , the contents of port p1 register is read. 1 : the contents of port p1 register is read always. in microprocessor mode and memory expansion mode, this register is valid in the following: ?external bus width is 8 bits. ?port p1 can be used as a port in multiplexed bus for the entire space.
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 171 rev. 1.0 M306H2MC-XXXFP figure 2.16.1 programmable i/o ports (1) p0 0 to p0 7 , p2 0 to p2 7 , p3 0 to p3 7 , p4 0 to p4 7 , p5 0 to p5 4 , p5 6 p1 0 to p1 4 p1 5 to p1 7 p5 7 , p6 0 , p6 1 , p6 4 , p6 5 , p7 2 to p7 6 , p8 0 , p8 1 , p9 0 , p9 2 data bus direction register pull-up selection port latch data bus direction register pull-up selection port latch port p1 control register direction register port latch port p1 control register pull-up selection data bus input to respective peripheral functions direction register port latch pull-up selection data bus input to respective peripheral functions note1 : symbolizes a parasitic diode. do not apply a voltage higher than vcc to each port. "1" output (note1) (note1) (note1) (note1) v cc v ss
172 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP figure 2.16.2 programmable i/o ports (2) p7 0 , p7 1 p8 5 p8 2 to p8 4 p5 5 , p6 2 , p6 6 , p7 7 , p9 1 , p9 7 p6 3 , p6 7 data bus direction register pull-up selection port latch input to respective peripheral functions data bus direction register pull-up selection port latch input to respective peripheral functions "1" output data bus direction register pull-up selection port latch data bus nmi interrupt input "1" output direction register port latch input to respective peripheral functions note1 : symbolizes a parasitic diode. do not apply a voltage higher than vcc to each port. (note1) (note1) (note1) (note1) (note1) v cc v ss data bus
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 173 rev. 1.0 M306H2MC-XXXFP figure 2.16.3 programmable i/o ports (3) p9 3 , p9 4 p9 6 p9 5 data bus direction register pull-up selection port latch analog input input to respective peripheral functions p10 0 to p10 3 (inside dotted-line not included) p10 4 to p10 7 (inside dotted-line included) d-a output enabled direction register pull-up selection port latch data bus input to respective peripheral functions d-a output enabled analog output "1" output direction register pull-up selection port latch data bus analog input "1" output direction register pull-up selection port latch data bus analog input input to respective peripheral functions note1 : symbolizes a parasitic diode. do not apply a voltage higher than vcc to each port. (note1) (note1) (note1) (note1) v cc v ss
174 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP figure 2.16.5 i/o pins figure 2.16.4 programmable i/o ports (4) p8 7 p8 6 fc rf rd data bus direction register pull-up selection port latch "1" output direction register pull-up selection port latch data bus note1 : symbolizes a parasitic diode. do not apply a voltage higher than vcc to each port. (note1) (note1) v cc v ss byte byte signal input cnv ss cnv ss signal input reset reset signal input note 1: symbolizes a parasitic diode. do not apply a voltage higher than vcc to each pin. (note1) (note1) (note1) v cc v ss m1, m2 input v cc v ss (note 1) to internal circuit
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 175 rev. 1.0 M306H2MC-XXXFP figure 2.16.6 direction register port pi direction register (note 1, 2) symbol address when reset pdi (i = 0 to 10, except 8) 03e2 16 , 03e3 16 , 03e6 16 , 03e7 16 , 03ea 16 00 16 00 16 03eb 16 , 03ee 16 , 03ef 16 , 03f3 16 , 03f6 16 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 pdi_0 port pi 0 direction register pdi_1 port pi 1 direction register pdi_2 port pi 2 direction register pdi_3 port pi 3 direction register pdi_4 port pi 4 direction register pdi_5 port pi 5 direction register pdi_6 port pi 6 direction register pdi_7 port pi 7 direction register 0 : input mode (functions as an input port) 1 : output mode (functions as an output port) (i = 0 to 10 except 8) port p8 direction register symbol address when reset pd8 03f2 16 00x00000 2 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 pd8_0 port p8 0 direction register pd8_1 port p8 1 direction register pd8_2 port p8 2 direction register pd8_3 port p8 3 direction register pd8_4 port p8 4 direction register nothing is assigned. in an attempt to write to this bit, write 0. the value, if read, turns out to be indeterminate. pd8_6 port p8 6 direction register pd8_7 port p8 7 direction register 0 : input mode (functions as an input port) 1 : output mode (functions as an output port) 0 : input mode (functions as an input port) 1 : output mode (functions as an output port) note 1: set bit 2 of protect register (address 000a 16 ) to 1 before rewriting to the port p9 direction register. note 2: in memory expansion and microprocessor mode, the contents of corresponding port pi direction register of pins a 0 to a 19 , d 0 to d 15 , cs0 to cs3, rd, wrl/wr, wrh/bhe, ale, rdy, hold, hlda and bclk cannot be modified.
176 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP figure 2.16.7 port register port pi register (note 2) symbol address when reset pi (i = 0 to 10, except 8) 03e0 16 , 03e1 16 , 03e4 16 , 03e5 16 , 03e8 16 indeterminate 03e9 16 , 03ec 16 , 03ed 16 , 03f1 16 , 03f4 16 indeterminate bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 pi_0 port pi 0 register pi_1 port pi 1 register pi_2 port pi 2 register pi_3 port pi 3 register pi_4 port pi 4 register pi_5 port pi 5 register pi_6 port pi 6 register pi_7 port pi 7 register data is input and output to and from each pin by reading and writing to and from each corresponding bit 0 : l level data 1 : h level data (note) (i = 0 to 10 except 8) port p8 register symbol address when reset p8 03f0 16 indeterminate bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 p8_0 port p8 0 register p8_1 port p8 1 register p8_2 port p8 2 register p8_3 port p8 3 register p8_4 port p8 4 register p8_5 port p8 5 register p8_6 port p8 6 register p8_7 port p8 7 register data is input and output to and from each pin by reading and writing to and from each corresponding bit (except for p8 5 ) 0 : l level data 1 : h level data note 1: since p7 0 and p7 1 are n-channel open drain ports, the data is high-impedance. note 2: in memory expansion and microprocessor mode, the contents of corresponding port pi direction register of pins a 0 to a 19 , d 0 to d 15 , cs0 to cs3, rd, wrl/wr, wrh/bhe, ale, rdy, hold, hlda and bclk cannot be modified.
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 177 rev. 1.0 M306H2MC-XXXFP figure 2.16.8 pull-up control register pull-up control register 0 symbol address when reset pur0 03fc 16 00 16 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 pu00 p0 0 to p0 3 pull-up pu01 p0 4 to p0 7 pull-up pu02 p1 0 to p1 3 pull-up pu03 p1 4 to p1 7 pull-up pu04 p2 0 to p2 3 pull-up pu05 p2 4 to p2 7 pull-up pu06 p3 0 to p3 3 pull-up pu07 p3 4 to p3 7 pull-up the corresponding port is pulled high with a pull-up resistor 0 : not pulled high 1 : pulled high pull-up control register 1 symbol address when reset pur1 03fd 16 00 16 (note 2) bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 pu10 p4 0 to p4 3 pull-up (note 3) pu11 p4 4 to p4 7 pull-up pu12 p5 0 to p5 3 pull-up (note 3) pu13 p5 4 to p5 7 pull-up (note 3) pu14 p6 0 to p6 3 pull-up pu15 p6 4 to p6 7 pull-up pu16 p7 0 to p7 3 pull-up (note 1) pu17 p7 4 to p7 7 pull-up the corresponding port is pulled high with a pull-up resistor 0 : not pulled high 1 : pulled high note 1: since p7 0 and p7 1 are n-channel open drain ports, pull-up is not available for them. note 2: when the v cc level is being impressed to the cnv ss terminal, this register becomes to 02 16 when reset (pu11 becomes to 1 ). note 3: in memory expansion and microprocessor mode,the content of these bits can be changed,but the pull-up resistance is not connected. pull-up control register 2 symbol address when reset pur2 03fe 16 00 16 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 pu20 p8 0 to p8 3 pull-up pu21 p8 4 to p8 7 pull-up (except p8 5 ) pu22 p9 0 to p9 3 pull-up pu23 p9 4 to p9 7 pull-up pu24 p10 0 to p10 3 pull-up pu25 p10 4 to p10 7 pull-up nothing is assigned. in an attempt to write to these bits, write 0 . the value, if read, turns out to be 0 . the corresponding port is pulled high with a pull-up resistor 0 : not pulled high 1 : pulled high
178 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP figure 2.16.9 port control register port control register symbpl address when reset pcr 03ff 16 00 16 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 pcr0 port p1 control register 0 : when input port, read port input level. when output port, read the contents of port p1 register. 1 : read the contents of port p1 register though input/output port. nothing is assigned. in an attempt to write to these bits, write 0 . the value, if read, turns out to be 0 . a a
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 179 rev. 1.0 M306H2MC-XXXFP table 2.16.1 example connection of unused pins in single-chip mode pin nameconnection ports p0 to p10 (excluding p8 5 ) after setting for input mode, connect every pin to v ss or v cc via a resistor; or after setting for output mode, leave these pins open. open x out (note) nmi connect via register to v cc (pull-up) connect to v cc av ss , v ref , byte av cc connect to v ss note: with external clock in p ut to x in p in. table 2.16.2 example connection of unused pins in memory expansion mode and microprocessor mode pin nameconnection ports p6 to p10 (excluding p8 5 ) av ss , v ref av cc after setting for input mode, connect every pin to v ss or v cc via a resistor; or after setting for output mode, leave these pins open. open connect to v cc connect to v ss note 1: with external clock input to x in pin. note 2: when the bclk output disable bit (bit 7 at address 0004 16 ) is set to 1, connect to v cc via a resistor (pull-up) . hold, rdy, nmi connect via resistor to v cc (pull-up) bhe, ale, hlda, x out (note1), bclk(note2) p4 5 /cs1 to p4 7 /cs3 sets ports to input mode, sets bits cs1 through cs3 to 0, and connects to vcc via resistors (pull-up). figure 2.16.10 example connection of unused pins n m i x o u t a v c c a v s s v r e f o p e n m i c r o c o m p u t e r v c c v s s h o l d r d y a l e b c l k b h e h l d a o p e n p o r t p 4 5 / c s 1 t o p 4 7 / c s 3 0 . 4 7 f c n v s s p o r t p 6 t o p 1 0 ( e x c e p t f o r p 8 5 ) ( i n p u t m o d e ) ( o u t p u t m o d e ) ( i n p u t m o d e ) . . . . . . b y t e a v s s v r e f m i c r o c o m p u t e r v c c v s s a v c c o p e n p o r t p 0 t o p 1 0 ( e x c e p t f o r p 8 5 ) ( i n p u t m o d e ) ( o u t p u t m o d e ) ( i n p u t m o d e ) . . . . . . n m i x o u t o p e n i n s i n g l e - c h i p m o d e i n m e m o r y e x p a m s i o n m o d e o r i n m i c r o p r o s s o r m o d e n ! : w h e n t h e b c l k o u t p u t d i s a b l e b i t ( b i t 7 a t a d d r e s s 0 0 0 4 1 6 ) i s s e t t o 1 , c o n n e t t o v c c v i a a r e s i s t o r ( p u l l - u p )
180 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP 3. usage precaution timer a (timer mode) (1) reading the timer ai register while a count is in progress allows reading, with arbitrary timing, the value of the counter. reading the timer ai register with the reload timing gets ?fff 16 ? reading the timer ai register after setting a value in the timer ai register with a count halted but before the counter starts counting gets a proper value. timer a (event counter mode) (1) reading the timer ai register while a count is in progress allows reading, with arbitrary timing, the value of the counter. reading the timer ai register with the reload timing gets ?fff 16 ?by underflow or ?000 16 ?by overflow. reading the timer ai register after setting a value in the timer ai register with a count halted but before the counter starts counting gets a proper value. (2) when stop counting in free run type, set timer again. (3) in the case of using ?vent counter mode?as ?ree-run type?for timer a, the timer register contents may be unkown when counting begins. if the timer register is set before counting has started, then the starting value will be unkown. this issue will occuer only for the ?vent counter mode?operating as ?ree-run type? the value of the timer register will not be unkown during counting. timer a (one-shot timer mode) (1) setting the count start flag to ??while a count is in progress causes as follows: ?the counter stops counting and a content of reload register is reloaded. ?the tai out pin outputs ??level. ?the interrupt request generated and the timer ai interrupt request bit goes to ?? (2) the timer ai interrupt request bit goes to ??if the timer's operation mode is set using any of the following procedures: ?selecting one-shot timer mode after reset. ?hanging operation mode from timer mode to one-shot timer mode. ?changing operation mode from event counter mode to one-shot timer mode. therefore, to use timer ai interrupt (interrupt request bit), set timer ai interrupt request bit to ??after the above listed changes have been made. timer a (pulse width modulation mode) (1) the timer ai interrupt request bit becomes ??if setting operation mode of the timer in compliance with any of the following procedures: ?selecting pwm mode after reset. ?hanging operation mode from timer mode to pwm mode. ?hanging operation mode from event counter mode to pwm mode. therefore, to use timer ai interrupt (interrupt request bit), set timer ai interrupt request bit to ??after the above listed changes have been made. (2) setting the count start flag to ??while pwm pulses are being output causes the counter to stop counting. if the tai out pin is outputting an ??level in this instance, the output level goes to ?? and the timer ai interrupt request bit goes to ?? if the tai out pin is outputting an ??level in this instance, the level does not change, and the timer ai interrupt request bit does not becomes ??
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 181 rev. 1.0 M306H2MC-XXXFP timer b (timer mode, event counter mode) (1) reading the timer bi register while a count is in progress allows reading , with arbitrary timing, the value of the counter. reading the timer bi register with the reload timing gets ?fff 16 ? reading the timer bi register after setting a value in the timer bi register with a count halted but before the counter starts counting gets a proper value. timer b (pulse period/pulse width measurement mode) (1) if changing the measurement mode select bit is set after a count is started, the timer bi interrupt request bit goes to ?? (2) when the first effective edge is input after a count is started, an indeterminate value is transferred to the reload register. at this time, timer bi interrupt request is not generated. a-d converter (1) write to each bit (except bit 6) of a-d control register 0, to each bit of a-d control register 1, and to bit 0 of a-d control register 2 when a-d conversion is stopped (before a trigger occurs). in particular, when the vref connection bit is changed from ??to ?? start a-d conversion after an elapse of 1 ? or longer. (2) when changing a-d operation mode, select analog input pin again. (3) using one-shot mode or single sweep mode read the correspondence a-d register after confirming a-d conversion is finished. (it is known by a-d conversion interrupt request bit.) (4) using repeat mode, repeat sweep mode 0 or repeat sweep mode 1 use the undivided main clock as the internal cpu clock. stop mode and wait mode ____________ (1) when returning from stop mode by hardware reset, reset pin must be set to ??level until main clock oscillation is stabilized. (2) when switching to either wait mode or stop mode, instructions occupying four bytes either from the wait instruction or from the instruction that sets the every-clock stop bit to ??within the instruction queue are prefetched and then the program stops. so put at least four nops in succession either to the wait instruction or to the instruction that sets the every-clock stop bit to ?? (3) when the mcu running in low-speed or low power dissipation mode, do not enter wait mode with wait periphheral function clock stop bit set to ?? interrupts (1) reading address 00000 16 ?when maskable interrupt is occurred, cpu read the interrupt information (the interrupt number and interrupt request level) in the interrupt sequence. the interrupt request bit of the certain interrupt written in address 00000 16 will then be set to ?? reading address 00000 16 by software sets enabled highest priority interrupt source request bit to ?? though the interrupt is generated, the interrupt routine may not be executed. do not read address 00000 16 by software. (2) setting the stack pointer ?the value of the stack pointer immediately after reset is initialized to 0000 16 . accepting an interrupt before setting a value in the stack pointer may become a factor of runaway. be sure to set a value in the stack pointer before accepting an interrupt. _______ when using the nmi interrupt, initialize the stack point at the beginning of a program. concerning the first in _______ struction immediately after reset, generating any interrupts including the nmi interrupt is prohib ited.
182 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP _______ (3) the nmi interrupt _______ ?as for the nmi interrupt pin, an interrupt cannot be disabled. connect it to the v cc pin via a resistor (pull-up) if unused. be sure to work on it. _______ ?do not get either into stop mode with the nmi pin set to ?? (4) external interrupt ________ ________ ?when the polarity of the int0 to int5 pins is changed, the interrupt request bit is sometimes set to ?? after changing the polarity, set the interrupt request bit to ?? (5) rewrite the interrupt control register ?to rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register. if there is possibility of the interrupt request occur, rewrite the interrupt control register after the interrupt is disabled. the program examples are described as follow: example 1: int_switch1: fclr i ; disable interrupts. and.b #00h, 0055h ; clear ta0ic int. priority level and int. request bit. nop ; four nop instructions are required when using hold function. nop fset i ; enable interrupts. example 2: int_switch2: fclr i ; disable interrupts. and.b #00h, 0055h ; clear ta0ic int. priority level and int. request bit. mov.w mem, r0 ; dummy read. fset i ; enable interrupts. example 3: int_switch3: pushc flg ; push flag register onto stack fclr i ; disable interrupts. and.b #00h, 0055h ; clear ta0ic int. priority level and int. request bit. popc flg ; enable interrupts. the reason why two nop instructions (four when using the hold function) or dummy read are inserted before fset i in examples 1 and 2 is to prevent the interrupt enable flag i from being set before the interrupt control register is rewritten due to effects of the instruction queue. ?when a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the interrupt request bit is not set sometimes even if the interrupt request for that register has been gener ated. this will depend on the instruction. if this creates problems, use the below instructions to change the register. instructions : and, or, bclr, bset electric characteristic differences between mask rom and flash memory version mcus there are differences in electric characteristics, operation margin, noise immunity, and noise radiation between mask rom and flash memory version mcus due to the difference in the manufacturing processes. when manufacturing an application system with the flash memory version and then switching to use of the mask rom version, please perform sufficient evaluations for the commercial samples of the mask rom version.
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 183 rev. 1.0 M306H2MC-XXXFP other notes (1) timing of power supplying the power need to supply to v cc , v dd 1, v dd 2, v dd 3 and av cc at a time. while operating, must set same voltage. (2) power supply noise and latch-up in order to avoid power supply noise and latch-up, connect a bypass capacitor (more than 0.1 f) directly between the v cc pin and v ss pin, v dd1 pin and v ss1 pin, v dd2 pin and v ss2 pin, v dd3 pin and v ss3 pin, av cc pin and av ss pin using a heavy wire. (3) when oscillation circuit stop for data slicer expansion register xtal-vco, pdc_vco_on,vps_vco_on is set at l , when the data slicer is not used, and the oscillation is stopped. when starting oscillation again, set data at the folowing order. (a) set expansion register xtal-vco = h . (b) set expansion register pdc_vco_on,vps_vco_on = h . (c) 60 ms or more is a waiting state (stability period of internal oscillation circuit + data slice preparation). to operate slice ram , set expansion register xtal_vco = h . and input 4.43 mhz sub carrier frequency clock from the fscin pin. access the memories after wating for 20 ms certainly when resuming synchronous oscillation from the off state , and begin to input clock into the fscin pin. (4) at stop mode (clock is stopped) set each input pins to as follows. (a) set m1 pin = v ss . (b) stop the fscin pin input. (c) set expansion register stby0 and stby1 = h . set all expansion registers to l except for the superscription register. (5) when operation start from stand-by mode (clock is stopped) input fscin pin clock after set l to register stby0 and stby1. at next, set expansion register as notes (3).
184 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP (6) notes on operating with a low supply voltage (v cc = 3.0 v) when in single-chip mode, this product can operate with a low supply voltage (v cc = 3.0 v) only during low power dissipation mode. before operating with a low supply voltage, always be sure to set the relevant register bits to select low power dissipation mode (bclk : f(x cin ), main clock x in : stop, subclock x cin : oscillating). then reduce the power supply voltage v cc to 3.0 v. also, when returning to normal operation, raise the power supply voltage to 5v while in low power consumption mode before entering normal operation mode. when moving from any operation mode to another, make sure a state transition occurs according to the state transition diagram (figure 2.5.5) in section 2.5.7, "power control." the status of the power supply voltage vcc during operation mode transition is shown in figure 3.1 below. figure 3.1 status of the power supply voltage vcc during operation mode transition l o w p o w e r dissipation m o d e n o r m a l o p e r a t i o n m o d e v c c 5 v 3 v p o w e r c o n t r o l o p e r a t i o n m o d e s n o t e 1 : n o r m a l o p e r a t i o n m o d e r e f e r s t o t h e h i g h - s p e e d , m e d i u m - s p e e d , a n d l o w - s p e e d m o d e s . n o t e 2 : w h e n o p e r a t i n g w i t h a l o w s u p p l y v o l t a g e , b e a w a r e t h a t o n l y t h e c p u , r o m , r a m , i n p u t / o u t p u t p o r t s , t i m e r s ( t i m e r s a a n d b ) , a n d t h e i n t e r r u p t c o n t r o l c i r c u i t c a n b e u s e d . a l l o t h e r i n t e r n a l r e s o u r c e s ( e . g . , d a t a s l i c e r , d m a c , a / d , a n d d / a ) c a n n o t b e u s e d . n o r m a l o p e r a t i o n m o d e
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 185 rev. 1.0 M306H2MC-XXXFP table 4.1 absolute maximum ratings v r e f , x i n , m 1 , m 2 x o u t , p 1 1 v o - 0 . 3 t o v c c + 0 . 3 - 0 . 3 t o v c c + 0 . 3 p d t a = 2 5 - 0 . 3 t o 5 . 7 5 - 0 . 3 t o 5 . 7 5 v v v v i a v c c v c c t s t g t o p r m w v - 4 0 t o 1 2 5 1 00 0 - 2 0 t o 7 0 p 3 0 t o p 3 7 , p 4 0 t o p 4 7 , p 5 0 t o p 5 7 , p 6 0 t o p 6 7 , p 7 2 t o p 7 7 , p 8 0 t o p 8 7 , p 0 0 t o p 0 7 , p 1 0 t o p 1 7 , p 2 0 t o p 2 7 , p 3 0 t o p 3 7 , p 4 0 t o p 4 7 , p 5 0 t o p 5 7 , p 6 0 t o p 6 7 , p 7 2 t o p 7 7 , p 8 0 t o p 8 4 , p 0 0 t o p 0 7 , p 1 0 t o p 1 7 , p 2 0 t o p 2 7 , r e s e t , p 9 0 t o p 9 7 , p 1 0 0 t o p 1 0 7 , p 8 6 , p 8 7 , p 9 0 t o p 9 7 , p 1 0 0 t o p 1 0 7 , p 7 0 , p 7 1 p 7 0 , p 7 1 - 0 . 3 t o 5 . 7 5 - 0 . 3 t o 5 . 7 5 v v c n v s s , b y t e , v c c = a v c c v c c = a v c c c c c s y m b o l p a r a m e t e r c o n d i t i o nr a t e d v a l u eu n i t s u p p l y v o l t a g e a n a l o g s u p p l y v o l t a g e i n p u t v o l t a g e o u t p u t v o l t a g e p o w e r d i s s i p a t i o n o p e r a t i n g a m b i e n t t e m p e r a t u r e s t o r a g e t e m p e r a t u r e 4. electrical characteristics
186 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP note 1: noise component is within 30mv. note 2: the mean output current is the mean value within 100ms. note 3: the total iol (peak) for ports p0, p1, p2, p8 6 , p8 7 , p9, and p10 must be 80ma max. the total i oh (peak) for ports p0, p1, p2, p8 6 , p8 7 , p9, and p10 must be 80ma max. the total iol (peak) for ports p3, p4, p5, p6, p7, and p8 0 to p8 4 must be 80ma max. the total ioh (peak) for ports p3, p4, p5, p6, p7 2 to p7 7 , and p8 0 to p8 4 must be 80ma max. note 4: use the low power dissipation mode. tabl 4.2 recommended operating conditions (referenced to v cc = 4.75v to 5.25v at ta = ?20 to 70 o c unless otherwise specified) p7 0 to p7 7 , p8 0 to p8 7 , p9 0 to p9 7 , p10 0 to p10 7 , p3 1 to p3 7 , p4 0 to p4 7 , p5 0 to p5 7, p6 0 to p6 7 , 4.75 5.25 vcc 5.0 vcc avcc v v 0 0 v ih vss avss 0.8vcc v v vcc v x in , reset, cnv ss , byte, m1, m2 symbol parameter unit standard min ty p. max. supply voltage analog supply voltage supply voltage analog supply voltage high input voltage i oh (avg) ma ma v 0.8vcc vcc i oh (peak) -5.0 -10.0 10.0 5.0 ma f(x in ) i ol (peak) ma i ol (avg) f (xc in ) khz 50 32.768 p00 to p0 7 , p10 to p1 7 ,p20 to p2 7 ,p30 to p3 7 , p40 to p4 7 , p50 to p5 7 ,p60 to p6 7 ,p70 to p7 7 , p80 to p8 4, p8 6, p8 7, p90 to p9 7, p100 to p10 7 , p11, mhz v v 0.2vcc 0 0 0 0.2vcc 0.16vcc x in , reset, cnv ss , byte, m1, m2 v il low input voltage high peak output current high average output current low peak output current low average output current main clock input oscillation frequency subclock oscillation frequency with wait no wait v cvin cvin, syncin v fscin input voltage fscin(note 1) 2v p-p 0.3v p-p 4.0v p-p v v composite video input voltage (note 2.3) vcc=4.75v to 5.25v vcc=2.80v to 5.25v (see note 4) 10 0 f( fscin ) mhz 4.434 oscillation frequency for synchronous signal(duty 40% to 60%) p0 0 to p0 7 , p1 0 to p1 7 , p2 0 to p2 7 , p3 0 (during single-chip mode) v 0.5vcc vcc p0 0 to p0 7 , p1 0 to p1 7 , p2 0 to p2 7 , p3 0 (data input function during memory expansion and microprocessor modes) p0 0 to p0 7 , p1 0 to p1 7 , p2 0 to p2 7 , p3 0 (during single-chip mode) v p0 0 to p0 7 , p1 0 to p1 7 , p2 0 to p2 7 , p3 0 (data input function during memory expansion and microprocessor modes) p00 to p0 7 , p10 to p1 7 ,p20 to p2 7 ,p30 to p3 7 , p40 to p4 7 , p50 to p5 7 ,p60 to p6 7 ,p7 2 to p7 7 , p80 to p8 4, p8 6, p8 7, p90 to p9 7, p100 to p10 7 , p11 p00 to p0 7 , p10 to p1 7 ,p20 to p2 7 ,p30 to p3 7 , p40 to p4 7 , p50 to p5 7 , p60 to p6 7 ,p70 to p7 7 , p80 to p8 4, p8 6, p8 7, p90 to p9 7, p100 to p10 7 , p11 p70 to p7 7 , p80 to p8 7 , p90 to p9 7 , p100 to p10 7 , p3 1 to p3 7 , p40 to p4 7 , p50 to p5 7, p60 to p6 7 , p0 0 to p0 7 , p10 to p1 7 ,p20 to p2 7 , p30 to p3 7 , p40 to p4 7 , p50 to p5 7 ,p60 to p6 7 , p7 2 to p7 7 , p80 to p8 4, p8 6, p8 7, p90 to p9 7, p100 to p10 7 , p11
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 187 rev. 1.0 M306H2MC-XXXFP table 4.3 electrical characteristics (1)v cc = 5v (referenced to v cc = 5v, v ss = 0v at ta = 25 o c, f(x in ) =10mh z unless otherwise specified) i i h i i l 5 . 0 a p 0 0 t o p 0 7 , p 1 0 t o p 1 7 , p 2 0 t o p 2 7 , p 3 0 t o p 3 7 , p 4 0 t o p 4 7 , p 5 0 t o p 5 7 , p 6 0 t o p 6 7 , p 7 0 t o p 7 7 , p 8 0 t o p 8 7 , p 9 0 t o p 9 7 , p 1 0 0 t o p 1 0 7 , x i n , r e s e t , c n v s s , b y t e , m 1 , m 2 v i = 5 v v i = 0 v-5 . 0 p 0 0 t o p 0 7 , p 1 0 t o p 1 7 , p 2 0 t o p 2 7 , p 3 0 t o p 3 7 , p 4 0 t o p 4 7 , p 5 0 t o p 5 7 , p 6 0 t o p 6 7 , p 7 0 t o p 7 7 , p 8 0 t o p 8 7 , p 9 0 t o p 9 7 , p 1 0 0 t o p 1 0 7 , x i n , r e s e t , c n v s s , b y t e , m 1 , m 2 r p u l l u p 5 0 . 0 p 0 0 t o p 0 7 , p 1 0 t o p 1 7 , p 2 0 t o p 2 7 , p 3 0 t o p 3 7 , p 4 0 t o p 4 7 , p 5 0 t o p 5 7 , p 6 0 t o p 6 7 , p 7 2 t o p 7 7 , p 8 0 t o p 8 4 , p 8 6 , p 8 7 , p 9 0 t o p 9 7 , p 1 0 0 t o p 1 0 7 v i = 0 v 3 0 . 01 6 7 . 0 v t + - v t - 0 . 21 . 8v r e s e t h y s t e r e s i s h i g h i n p u t c u r r e n t l o w i n p u t c u r r e n t p u l l - u p r e s i s t a n c e a 1 . 2v v s y n c i n 0 . 30 . 6 1 . 4v v d a t ( t e x t ) 0 . 60 . 9 % ? f / f 7 1 7 .0 kh z f h 1 4 . 6 1 5 . 6 2 5 sy n c v o l t a g e a m p l i t u d e t e l e t e x t d a t a v o l t a g e a m p l i t u d e r a n g e f o r d i s p l a y o s c i l l a t o r c i r c u i t h o r i z o n t a l s y n c h r o n o u s s i g n a l f r e q u e n c y v t + - v t - 0 . 21 . 4v c t s 0 , c l k 0 h y s t e r e s i s v o h v o h v o h v o l v o l v o l v v 4 . 7 v x o u t 3 . 0 3 . 0 v 2 . 0 0 . 4 5v v x o u t 2 . 0 2 . 0 3 . 0 i o h =-5 m a i o h =-1 m a i o h =- 2 0 0 a i o h =-0 . 5 m a i o l = 5 m a i o l = 1 m a i o l = 2 0 0 a i o l = 0 . 5 m a p 0 0 t o p 0 7 , p 1 0 t o p 1 7 , p 2 0 t o p 2 7 , p 0 0 t o p 0 7 , p 1 0 t o p 1 7 , p 2 0 t o p 2 7 , p 3 0 t o p 3 7 , p 4 0 t o p 4 7 , p 5 0 t o p 5 7 , p 3 0 t o p 3 7 , p 4 0 t o p 4 7 , p 5 0 t o p 5 7 , p 6 0 t o p 6 7 , p 7 2 t o p 7 7 , p 8 0 t o p 8 4 , p 0 0 t o p 0 7 , p 1 0 t o p 1 7 , p 2 0 t o p 2 7 , p 3 0 t o p 3 7 , p 4 0 t o p 4 7 , p 5 0 t o p 5 7 , p 6 0 t o p 6 7 , p 7 2 t o p 7 7 , p 8 0 t o p 8 4 , h i g h p o w e r l o w p o w e r p 8 6 , p 8 7 , p 9 0 t o p 9 7 , p 1 0 0 t o p 1 0 7 , h i g h p o w e r l o w p o w e r p 6 0 t o p 6 7 , p 7 0 t o p 7 7 , p 8 0 t o p 8 4 , p 8 6 , p 8 7 , p 9 0 t o p 9 7 , p 1 0 0 t o p 1 0 7 , p 8 6 , p 8 7 , p 9 0 t o p 9 7 , p 1 0 0 t o p 1 0 7 , h i g h p o w e r l o w p o w e r x c o u t 3 . 0 1 . 6 v p 0 0 t o p 0 7 , p 1 0 t o p 1 7 , p 2 0 t o p 2 7 , p 3 0 t o p 3 7 , p 4 0 t o p 4 7 , p 5 0 t o p 5 7 , p 6 0 t o p 6 7 , p 7 0 t o p 7 7 , p 8 0 t o p 8 4 , p 8 6 , p 8 7 , p 9 0 t o p 9 7 , p 1 0 0 t o p 1 0 7 , v t + - v t - t a 2 o u t t o t a 4 o u t , k i 0 t o k i 3 0 . 20 . 8v t b 0 i n t o t b 2 i n , i n t 0 t o i n t 5 , a d t r g , c t s 1 , c l k 1 , n m i h o l d , r d y , t a 0 i n t o t a 4 i n , v x c o u t 0 0 h i g h p o w e r l o w p o w e r s y m b o l p a r a m e t e r u n i t s t a n d a r d m i nt y p .m a x . h i g h o u t p u t v o l t a g e h i g h o u t p u t v o l t a g e h i g h o u t p u t v o l t a g e h i g h o u t p u t v o l t a g e l o w o u t p u t v o l t a g e l o w o u t p u t v o l t a g e l o w o u t p u t v o l t a g e l o w o u t p u t v o l t a g e h y s t e r e s i s w i t h n o l o a d a p p l i e d w i t h n o l o a d a p p l i e d w i t h n o l o a d a p p l i e d w i t h n o l o a d a p p l i e d m e a s u r i n g c o n d i t i o n p 1 1 p 1 1 lp2 t o lp 4 v c c = 4 . 7 5 v , i o h = -0.05ma 3 . 7 5v p 1 1 p 1 1 lp2 t o lp 4v c c = 4 . 7 5 v , i o l = 0.05ma 0 . 4v v o h h i g h o u t p u t v o l t a g e v o l l o w o u t p u t v o l t a g e k ?
188 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP v oh v 2.5 i oh = C150 a v oh v ol v 0.5 i ol =150 a highpower lowpower x cout with no load applied with no load applied 3.0 1.6 v p0 0 to p0 7 , p1 0 to p1 7 , p2 0 to p2 7 , p3 0 to p3 7 , p4 0 to p4 7 , p5 0 to p5 7 , p6 0 to p6 7 , p7 2 to p7 7 , p8 0 to p8 4 , p8 6 , p8 7 , p9 0 to p9 7 , p10 0 to p10 7 p11 p0 0 to p0 7 , p1 0 to p1 7 , p2 0 to p2 7 , p3 0 to p3 7 , p4 0 to p4 7 , p5 0 to p5 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 4 , p8 6 , p8 7 , p9 0 to p9 7 , p10 0 to p10 7 p11 v ol v t+- v t - 0.2 0.8 v ta2 out to ta4 out , nmi, ki 0 to ki 3 tb0 in to tb2 in , int 0 to int 5 , ta0 in to ta4 in , v x cout 0 0 with no load applied with no load applied highpower lowpower i ih 4.0 a p0 0 to p0 7 , p1 0 to p1 7 , p2 0 to p2 7 , p3 0 to p3 7 , p4 0 to p4 7 , p5 0 to p5 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , p9 0 to p9 7 , p10 0 to p10 7, x in , reset, cnvss, byte, m1, m2 v i =3v i il a v i =0v C4.0 p0 0 to p0 7 , p1 0 to p1 7 , p2 0 to p2 7 , p3 0 to p3 7 , p4 0 to p4 7 , p5 0 to p5 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , p9 0 to p9 7 , p10 0 to p10 7, x in , reset, cnvss, byte, m1, m2 r pullup v i =0v 120.0 k ? 66.0 500.0 symbol parameter unit standard min typ. max. measuring condition high output voltage high input voltage low input voltage high output voltage low output voltage low output voltage hysteresis pull-up resistance p0 0 to p0 7 , p1 0 to p1 7 , p2 0 to p2 7 , p3 0 to p3 7 , p4 0 to p4 7 , p5 0 to p5 7 , p6 0 to p6 7 , p7 2 to p7 7 , p8 0 to p8 4 , p8 6 , p8 7 , p9 0 to p9 7 , p10 0 to p10 7 table 4.4 electrical characteristics (2)v cc = 3v (referenced to v cc =3v,v ss =0v,ta=25c, f(x cin )=32kh z unless otherwise specified)
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 189 rev. 1.0 M306H2MC-XXXFP table 4.5 electrical characteristics (referenced to v cc = 5v, v ss = 0v at ta = 25 o c unless otherwise specified) symbol parameter unit standard min typ. max. measuring condition r rx cin v ram v fxin fxcin x in 6.0 1.0 feedback resistance feedback resistance ram retention voltage when clock is stopped i cc power supply current m ? ? tabl 4.6 video signal input conditions (v cc = 5.0v, ta = ?0 to 70 o c) symbol parameter unit standard min typ. max. measuring condition v v in-cu 1.0 composite video signal input clamp voltage sync-chip voltage note 1: this is a state where only one timer is operating with fc32 while the oscillation capability is set to low and slicer operation is turned off. note 2: v dd1 , v dd2 , and v dd3 all are at the same potential level as v cc . extension register (address 00 16 dd8) stby0 and (address 15 16 dd13) stby1 are set to 1 while all other extension registers (addresses 00 16 through 22 16 ) are set to 0. clock input to the fscin pin is disabled. inputs to the syncin and cvin1 pins are disabled.
190 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP table 4.7 a-d conversion characteristics (referenced to v cc = av cc = v ref = 5v, vss = av ss = 0v at ta = 25 o c, f(x in ) = 10mh z unless otherwise specified) table 4.8 d-a conversion characteristics (referenced to v cc = 5v, v ss = av ss = 0v, v ref = 5v at ta = 25 o c, f(x in ) = 10mh z unless otherwise specified) note: this applies when using one d-a converter, with the d-a register for the unused d-a converter set to ? 00 16 ? . the a-d converter's ladder resistance is not included. also, when the vref is unconnected at the a-d control register, iv ref is sent. s t a n d a r d m i n .t y p .m a x . r e s o l u t i o n a b s o l u t e a c c u r a c y b i t s l s b v r e f = v c c ? ?
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 191 rev. 1.0 M306H2MC-XXXFP timing requirements (referenced to v cc = 5v, v ss = 0v at ta = 25 o c unless otherwise specified) table 4.9 external clock input table 4.10 in memory expansion and microprocessor modes max. external clock rise time ns t r min. external clock input cycle time external clock input high pulse width external clock input low pulse width external clock fall time ns ns ns ns t c t w(h ) t w(l) t f parameter symbol unit standard 18 100 40 40 18 f(bclk) x 2 (note) (note) (note) 40 30 0 0 40 0 note: calculated according to the bclk frequency as follows: 40 min. data input setup time ns t su(db-rd) t su(rdy-bclk ) parameter symbol unit max. standard ns rdy input setup time data input hold time ns t h(rd-db) t h(bclk -rdy) ns rdy input hold time ns hold input setup time t su(hold-bclk ) ns hold input hold time t h(bclk-hold ) data input access time (no wait) ns t ac1(rd-db) ns ns t ac2(rd-db) t ac3(rd-db) data input access time (with wait) data input access time (when accessing multiplex bus area) ns t d(bclk-hlda ) hlda output delay time t ac1(rd ?db) = f(bclk) x 2 ?45 10 9 [ns] t ac2(rd ?db) = f(bclk) x 2 ?45 3 x 10 9 [ns] t ac3(rd ?db) = ?45 3 x 10 9 [ns]
192 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP standard max. ns tai in input low pulse width t w(tal) min. ns ns unit standard max. min. ns ns ns unit standard max. min. ns ns ns unit standard max. min. ns ns unit standard max. min. ns ns ns unit ns ns tai in input high pulse width t w(tah) parameter symbol tai in input cycle time tai in input high pulse width tai in input low pulse width t c(ta) t w(tah) t w(tal) symbol parameter tai in input cycle time tai in input high pulse width tai in input low pulse width t c(ta) t w(tah) t w(tal) symbol parameter t w(tah) t w(tal) symbol parameter tai in input high pulse width tai in input low pulse width symbol parameter t c(ta) tai in input cycle time tai out input cycle time tai out input high pulse width tai out input low pulse width tai out input setup time tai out input hold time t c(up) t w(uph) t w(upl) t su(up-t in ) t h(t in- up) 40 100 40 400 200 200 200 100 100 100 100 2000 1000 1000 400 400 timing requirements (referenced to v cc = 5v, v ss = 0v at ta = 25 o c unless otherwise specified) table 4.11 timer a input (counter input in event counter mode) table 4.12 timer a input (gating input in timer mode) table 4.13 timer a input (external trigger input in one-shot timer mode) table 4.14 timer a input (external trigger input in pulse width modulation mode) table 4.15 timer a input (up/down input in event counter mode)
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 193 rev. 1.0 M306H2MC-XXXFP timing requirements (referenced to v cc = 5v, v ss = 0v at ta = 25 o c unless otherwise specified) table 4.16 timer b input (counter input in event counter mode) ns ns ns ns ns ns ns standard max. min. tbi in input cycle time (counted on one edge) tbi in input high pulse width (counted on one edge) tbi in input low pulse width (counted on one edge) ns ns ns t c(tb) t w(tbh) t w(tbl) parameter symbol unit t c(tb) t w(tbl) t w(tbh) ns ns ns tbi in input high pulse width (counted on both edges) tbi in input low pulse width (counted on both edges) tbi in input cycle time (counted on both edges) standard max. min. ns ns t c(tb) t w(tbh) symbol parameter unit t w(tbl) ns tbi in input high pulse width tbi in input cycle time tbi in input low pulse width standard max. min. ns ns t c(tb) symbol parameter unit t w(tbl) ns t w(tbh) tbi in input cycle time tbi in input high pulse width tbi in input low pulse width standard max. min. ns ns t c(ad) t w(adl) symbol parameter unit ad trg input cycle time (trigger able minimum) ad trg input low pulse width standard max. min. ns ns t w(inh) t w(inl) symbol parameter unit inti input low pulse width inti input high pulse width standard max. min. clki input cycle time clki input high pulse width clki input low pulse width t c(ck) t w(ckh) t w(ckl) parameter symbol unit t d(c-q) t su(d-c) t h(c-q) txdi hold time rxdi input setup time txdi output delay time t h(c-d) rxdi input hold time 100 40 40 80 80 200 400 200 200 400 200 200 1000 125 250 250 200 100 100 0 30 90 80 table 4.17 timer b input (pulse period measurement mode) table 4.18 timer b input (pulse width measurement mode) table 4.19 a-d trigger input table 4.20 serial i/o _______ table 4.21 external interrupt inti inputs
194 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP s y m b o l s t a n d a r d m e a s u r i n g c o n d i t i o n m a x . m i n . p a r a m e t e ru n i t t d ( b c l k - a d ) a d d r e s s o u t p u t d e l a y t i m e4 0n s t h ( b c l k - a d ) a d d r e s s o u t p u t h o l d t i m e ( b c l k s t a n d a r d )4n s t h ( b c l k - c s ) c h i p s e l e c t o u t p u t h o l d t i m e ( b c l k s t a n d a r d )4n s t d ( b c l k - a l e ) a l e s i g n a l o u t p u t d e l a y t i m e4 0n s t h ( b c l k - a l e ) a l e s i g n a l o u t p u t h o l d t i m e 4n s t d ( b c l k - r d ) r d s i g n a l o u t p u t d e l a y t i m e4 0n s t h ( b c l k - r d ) r d s i g n a l o u t p u t h o l d t i m e0n s t d ( b c l k - w r ) w r s i g n a l o u t p u t d e l a y t i m e4 0n s t h ( b c l k - w r ) w r s i g n a l o u t p u t h o l d t i m e0n s t d ( b c l k - d b ) d a t a o u t p u t d e l a y t i m e ( b c l k s t a n d a r d )40n s t h ( b c l k - d b ) d a t a o u t p u t h o l d t i m e ( b c l k s t a n d a r d )4n s t h ( w r - d b ) d a t a o u t p u t h o l d t i m e ( w r s t a n d a r d ) ( n o t e 2 )0n s t d ( d b - w r ) d a t a o u t p u t d e l a y t i m e ( w r s t a n d a r d )n s ( n o t e 1 ) n o t e 1 : c a l c u l a t e d a c c o r d i n g t o t h e b c l k f r e q u e n c y a s f o l l o w s : t d ( d b w r ) = f ( b c l k ) x 2 1 0 9 4 0 [ n s ] t d ( b c l k - c s ) c h i p s e l e c t o u t p u t d e l a y t i m e4 0n s t h ( r d - a d ) a d d r e s s o u t p u t h o l d t i m e ( r d s t a n d a r d )0n s t h ( w r - a d ) a d d r e s s o u t p u t h o l d t i m e ( w r s t a n d a r d )0n s n o t e 2 : t h i s i s s t a n d a r d v a l u e s h o w s t h e t i m i n g w h e n t h e o u t p u t i s o f f , a n d d o e s n ' t s h o w h o l d t i m e o f d a t a b u s . h o l d t i m e o f d a t a b u s i s d i f f e r e n t b y c a p a c i t o r v o l u m e a n d p u l l - u p ( p u l l - d o w n ) r e s i s t a n c e v a l u e . h o l d t i m e o f d a t a b u s i s e x p r e s s e d i n t = c r x l n ( 1 v o l / v c c ) b y a c i r c u i t o f t h e r i g h t f i g u r e . f o r e x a m p l e , w h e n v o l = 0 . 2 v c c , c = 3 0 p f , r = 1 k ? , h o l d t i m e o f o u t p u t l l e v e l i s t = 3 0 p f x 1 k ? x l n ( 1 0 . 2 v c c / v c c ) = 6 . 7 n s . d b i r c f i g u r e 4 . 1 switching characteristics (referenced to v cc = 5v, v ss = 0v at ta = 25 o c, cm15 = ??unless otherwise specified) table 4.22 in memory expansion and microprocessor modes (no wait)
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 195 rev. 1.0 M306H2MC-XXXFP s y m b o l s t a n d a r d m e a s u r i n g c o n d i t i o n m a x . m i n . p a r a m e t e ru n i t t d ( b c l k - a d ) a d d r e s s o u t p u t d e l a y t i m e4 0n s t h ( b c l k - a d ) a d d r e s s o u t p u t h o l d t i m e ( b c l k s t a n d a r d )4n s t h ( b c l k - c s ) c h i p s e l e c t o u t p u t h o l d t i m e ( b c l k s t a n d a r d )4n s t d ( b c l k - a l e ) a l e s i g n a l o u t p u t d e l a y t i m e4 0n s t h ( b c l k - a l e ) a l e s i g n a l o u t p u t h o l d t i m eC 4n s t d ( b c l k - r d ) r d s i g n a l o u t p u t d e l a y t i m e4 0n s t h ( b c l k - r d ) r d s i g n a l o u t p u t h o l d t i m e0n s t d ( b c l k - w r ) w r s i g n a l o u t p u t d e l a y t i m e4 0n s t h ( b c l k - w r ) w r s i g n a l o u t p u t h o l d t i m e0n s t d ( b c l k - d b ) d a t a o u t p u t d e l a y t i m e ( b c l k s t a n d a r d )40n s t h ( b c l k - d b ) d a t a o u t p u t h o l d t i m e ( b c l k s t a n d a r d )4n s t h ( w r - d b ) d a t a o u t p u t h o l d t i m e ( w r s t a n d a r d ) ( n o t e 2 )0n s t d ( d b - w r ) d a t a o u t p u t d e l a y t i m e ( w r s t a n d a r d ) n s ( n o t e 1 ) n o t e 1 : c a l c u l a t e d a c c o r d i n g t o t h e b c l k f r e q u e n c y a s f o l l o w s : t d ( d b C w r ) = f ( b c l k ) 1 0 9 C 4 0 [ n s ] t d ( b c l k - c s ) c h i p s e l e c t o u t p u t d e l a y t i m e4 0n s t h ( r d - a d ) a d d r e s s o u t p u t h o l d t i m e ( r d s t a n d a r d )0n s t h ( w r - a d ) a d d r e s s o u t p u t h o l d t i m e ( w r s t a n d a r d )0n s n o t e 2 : t h i s i s s t a n d a r d v a l u e s h o w s t h e t i m i n g w h e n t h e o u t p u t i s o f f , a n d d o e s n ' t s h o w h o l d t i m e o f d a t a b u s . h o l d t i m e o f d a t a b u s i s d i f f e r e n t b y c a p a c i t o r v o l u m e a n d p u l l - u p ( p u l l - d o w n ) r e s i s t a n c e v a l u e . h o l d t i m e o f d a t a b u s i s e x p r e s s e d i n t = C c r x l n ( 1 C v o l / v c c ) b y a c i r c u i t o f t h e r i g h t f i g u r e . f o r e x a m p l e , w h e n v o l = 0 . 2 v c c , c = 3 0 p f , r = 1 k ? , h o l d t i m e o f o u t p u t l l e v e l i s t = C 3 0 p f x 1 k ? x l n ( 1 C 0 . 2 v c c / v c c ) = 6 . 7 s . d b i r c f i g u r e 4 . 1 switching characteristics (refer to v cc = 5v, v ss = 0v at ta = 25 o c, cm15 = 1 unless otherwise specified) table 4.23 in memory expansion and microprocessor modes (with wait, accessing external memory)
196 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP s y m b o l s t a n d a r d m e a s u r i n g c o n d i t i o n m a x . m i n . p a r a m e t e ru n i t t d ( b c l k - a d ) a d d r e s s o u t p u t d e l a y t i m e4 0n s t h ( b c l k - a d ) a d d r e s s o u t p u t h o l d t i m e ( b c l k s t a n d a r d )4n s t d ( b c l k - c s ) c h i p s e l e c t o u t p u t d e l a y t i m e4 0n s t h ( b c l k - c s ) c h i p s e l e c t o u t p u t h o l d t i m e ( b c l k s t a n d a r d )4n s n s t h ( r d - a d ) a d d r e s s o u t p u t h o l d t i m e ( r d s t a n d a r d ) ( n o t e ) t d ( b c l k - r d ) r d s i g n a l o u t p u t d e l a y t i m e4 0n s t h ( b c l k - r d ) r d s i g n a l o u t p u t h o l d t i m e0n s n s t h ( w r - a d ) a d d r e s s o u t p u t h o l d t i m e ( w r s t a n d a r d ) ( n o t e ) t d ( b c l k - w r ) w r s i g n a l o u t p u t d e l a y t i m e4 0n s t d ( b c l k - d b ) d a t a o u t p u t d e l a y t i m e ( b c l k s t a n d a r d )4 0n s t h ( b c l k - d b ) d a t a o u t p u t h o l d t i m e ( b c l k s t a n d a r d )4n s t d ( d b - w r ) d a t a o u t p u t d e l a y t i m e ( w r s t a n d a r d ) ( n o t e ) n s t d ( b c l k - a l e ) a l e s i g n a l o u t p u t d e l a y t i m e ( b c l k s t a n d a r d )4 0n s t h ( b c l k - a l e ) a l e s i g n a l o u t p u t h o l d t i m e ( b c l k s t a n d a r d ) 4n s t h ( a l e - a d ) a l e s i g n a l o u t p u t h o l d t i m e ( a d d e r s s s t a n d a r d )5 0n s t h ( b c l k - w r ) w r s i g n a l o u t p u t h o l d t i m e0n s n s t h ( r d - c s ) c h i p s e l e c t o u t p u t h o l d t i m e ( r d s t a n d a r d ) ( n o t e ) t h ( w r - c s ) c h i p s e l e c t o u t p u t h o l d t i m e ( w r s t a n d a r d ) ( n o t e ) n s t d ( a d - r d ) p o s t - a d d r e s s r d s i g n a l o u t p u t d e l a y t i m en s 0 t d ( a d - w r ) p o s t - a d d r e s s w r s i g n a l o u t p u t d e l a y t i m en s 0 t d z ( r d - a d ) a d d r e s s o u t p u t f l o a t i n g s t a r t t i m en s 8 t h ( w r - d b ) d a t a o u t p u t h o l d t i m e ( w r s t a n d a r d )n s ( n o t e ) n o t e : c a l c u l a t e d a c c o r d i n g t o t h e b c l k f r e q u e n c y a s f o l l o w s : t h ( r d a d ) = f ( b c l k ) x 2 1 0 9 [ n s ] t h ( w r a d ) = f ( b c l k ) x 2 1 0 9 [ n s ] t h ( r d c s ) = f ( b c l k ) x 2 1 0 9 [ n s ] t h ( w r c s ) = f ( b c l k ) x 2 1 0 9 [ n s ] t d ( d b w r ) = f ( b c l k ) x 2 1 0 9 4 0 [ n s ] x 3 t d ( a d a l e ) = f ( b c l k ) x 2 1 0 9 4 0 [ n s ] t h ( w r d b ) = f ( b c l k ) x 2 1 0 9 [ n s ] t d ( a d - a l e ) a l e s i g n a l o u t p u t d e l a y t i m e ( a d d r e s s s t a n d a r d )n s ( n o t e ) f i g u r e 4 . 1 switching characteristics (referenced to v cc = 5v, v ss = 0v at ta = 25 o c, cm15 = ??unless otherwise specified) table 4.24 in memory expansion and microprocessor modes (with wait, accessing external memory, multiplex bus area selected)
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 197 rev. 1.0 M306H2MC-XXXFP figure 4.1 port p0 to p11 measurement circuit p6 p7 p8 p10 p9 p0 p1 p2 p3 p4 p5 30pf p11
198 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP t su(d?) tai in input tai out input during event counter mode tbi in input clki txdi rxdi t c(ta) t w(tah) t w(tal) t c(up) t w(uph) t w(upl) t c(tb) t w(tbh) t w(tbl) t c(ad) t w(adl) t c(ck) t w(ckh) t w(ckl) t w(inl) t w(inh) t d(c?) t h(c?) t h(c?) t h(t in ?p) t su(up? in ) tai in input (when count on falling edge is selected) tai in input (when count on rising edge is selected) tai out input (up/down input) inti input ad trg input figure 4.2 timing diagram (1)
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 199 rev. 1.0 M306H2MC-XXXFP m e a s u r i n g c o n d i t i o n s : v c c = 5 v i n p u t t i m i n g v o l t a g e : d e t e r m i n e d w i t h v i l = 1 . 0 v , v i h = 4 . 0 v o u t p u t t i m i n g v o l t a g e : d e t e r m i n e d w i t h v o l = 2 . 5 v , v o h = 2 . 5 v b c l k h o l d i n p u t h l d a o u t p u t p 0 , p 1 , p 2 , p 3 , p 4 , p 5 0 t o p 5 2 v a l i d w i t h o r w i t h o u t w a i t n o t e : t h e a b o v e p i n s a r e s e t t o h i g h - i m p e d a n c e r e g a r d l e s s o f t h e i n p u t l e v e l o f t h e b y t e p i n a n d b i t ( p m 0 6 ) o f p r o c e s s o r m o d e r e g i s t e r 0 s e l e c t s t h e f u n c t i o n o f p o r t s p 4 0 t o p 4 3 . t h ( b c l k h o l d ) t s u ( h o l d b c l k ) i n m e m o r y e x p a n s i o n a n d m i c r o p r o c e s s o r m o d e s v a l i d o n l y w i t h w a i t t d ( b c l k h l d a ) t d ( b c l k h l d a ) h i z r d y i n p u t t s u ( r d y b c l k ) t h ( b c l k r d y ) b c l k r d ( m u l t i p l e x e d b u s ) ( m u l t i p l e x e d b u s ) w r , w r l , w r h w r , w r l , w r h ( s e p a r a t e b u s ) r d ( s e p a r a t e b u s ) figure 4.3 timing diagram (2)
200 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP b c l k c s i a l e 4 n s . m i n r d 4 0n s . m a x 0 n s . m i n 4 n s . m i n 4 n s . m i n h i z d b 0 n s . m i n a d i b h e r e a d t i m i n g b c l k c s i a l e 4 0n s . m a x 0 n s . m i n 4 n s . m i n 4 n s . m i n h i - z d b 4 0 n s . m a x 4 n s . m i n ( t c y c / 2 4 0 ) n s . m i n a d i b h e w r i t e t i m i n g t d ( b c l k a d ) t d ( b c l k a l e ) t h ( b c l k a l e ) t s u ( d b r d ) t h ( b c l k - a d ) t d ( b c l k w r ) t h ( b c l k d b ) t d ( b c l k r d ) t d ( b c l k a l e ) 4 0 n s . m i n t a c 1 ( r d d b ) i n m e m o r y e x p a n s i o n a n d m i c r o p r o c e s s o r m o d e s ( w i t h n o w a i t ) w r , w r l , w r h t d ( b c l k c s ) 4 0n s . m a x t c y c t h ( b c l k c s ) t h ( r d c s ) 0 n s . m i n 4 0n s . m a x t h ( b c l k a d ) t h ( r d a d ) 0 n s . m i n t h ( b c l k r d ) 2 5 n s . m a x t h ( r d d b ) t d ( b c l k c s ) 4 0n s . m a x t h ( b c l k c s ) t c y c t h ( w r c s ) 0 n s . m i n t d ( b c l k a d ) 4 0n s . m a x 4 0n s . m a x t h ( b c l k a l e ) 4 n s . m i n t h ( w r a d ) 0 n s . m i n t h ( b c l k w r ) t d ( b c l k d b ) t d ( d b w r ) t h ( w r d b ) 0 n s . m i n figure 4.4 timing diagram (3)
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 201 rev. 1.0 M306H2MC-XXXFP b c l k c s i a l e r d 4 n s . m i n h i z d b 4 0 n s . m i n 0 n s . m i n a d i b h e r e a d t i m i n g b c l k c s i a l e 4 n s . m i n t h ( w r a d ) a d i b h e ( t c y c 4 0 ) n s . m i n 0 n s . m i n d b i w r i t e t i m i n g t d ( b c l k r d ) 0 n s . m i n 0 n s . m i n t h ( r d a d ) i n m e m o r y e x p a n s i o n a n d m i c r o p r o c e s s o r m o d e s ( w h e n a c c e s s i n g e x t e r n a l m e m o r y a r e a w i t h w a i t ) m e a s u r i n g c o n d i t i o n s : v c c = 5 v i n p u t t i m i n g v o l t a g e : d e t e r m i n e d w i t h : v i l = 0 . 8 v , v i h = 2 . 5 v o u t p u t t i m i n g v o l t a g e : d e t e r m i n e d w i t h : v o l = 0 . 8 v , v o h = 2 . 0 v w r , w r l , w r h t d ( b c l k c s ) 4 0n s . m a x t c y c t h ( b c l k c s ) 4 n s . m i n t h ( r d c s ) 0 n s . m i n t h ( b c l k a d ) t d ( b c l k a d ) 4 0n s . m a x t d ( b c l k a l e ) 4 0n s . m a x t h ( b c l k a l e ) 4 n s . m i n t h ( b c l k r d ) 0 n s . m i n 4 0n s . m a x t a c 2 ( r d d b ) t h ( r d d b ) t s u ( d b r d ) t d ( b c l k c s ) 4 0n s . m a x t c y c t h ( b c l k c s ) 4 n s . m i n t h ( w r c s ) 0 n s . m i n t h ( b c l k a d ) t d ( b c l k a d ) 4 0n s . m a x t d ( b c l k a l e ) 4 0n s . m a x t h ( b c l k a l e ) 4 n s . m i n t h ( b c l k w r ) 0 n s . m i n t d ( b c l k w r ) 4 0n s . m a x t h ( b c l k d b ) 4 n s . m i n t d ( b c l k d b ) 4 0 n s . m a x t d ( d b w r ) t h ( w r d b ) figure 4.5 timing diagram (4)
202 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP i n m e m o r y e x p a n s i o n a n d m i c r o p r o c e s s o r m o d e s (w h e n a c c e s s i n g e x t e r n a l m e m o r y a r e a w i t h w a i t , a n d s e l e c t m u l t i p l e x e d b u s ) b c l k c s i a l e r d 4 n s . m i n t c y c a d i b h e a d i / d b i t d ( a d a l e ) r e a d t i m i n g 0 n s . m i n b c l k c s i a l e 4 n s . m i n 4 n s . m i n 4 n s . m i n t c y c a d i b h e a d i / d b i w r i t e t i m i n g a d d r e s s m e a s u r i n g c o n d i t i o n s : v c c = 5 v i n p u t t i m i n g v o l t a g e : d e t e r m i n e d w i t h v i l = 0 . 8 v , v i h = 2 . 5 v o u t p u t t i m i n g v o l t a g e : d e t e r m i n e d w i t h v o l = 0 . 8 v , v o h = 2 . 0 v ( t c y c / 2 ) n s . m i n a d d r e s s d a t a i n p u t ( t c y c / 2 ) n s . m i n t d ( b c l k a l e ) ( t c y c / 2 ) n s . m i n t h ( w r c s ) a d d r e s s ( t c y c * 3 / 2 4 0 ) n s . m i n t d ( b c l k a l e ) ( t c y c / 2 ) n s . m i n ( t c y c / 2 - 4 0 ) n s . m i n a d d r e s s 4 0n s . m a x t s u ( d b r d ) t a c 3 ( r d d b ) ( t c y c / 2 ) n s . m i n t h ( a l e a d ) 3 0 n s . m i n t d ( a d r d ) 0 n s . m i n t d z ( r d a d ) 8 n s . m a x t d ( a d w r ) 0 n s . m i n d a t a o u t p u t w r , w r l , w r h t d ( b c l k c s ) 4 0n s . m a x t h ( r d c s ) t h ( b c l k c s ) 4 n s . m i n t h ( b c l k a d ) t h ( r d d b ) 0 n s . m i n 4 0 n s . m i n 4 0n s . m a x t d ( b c l k a d ) 4 n s . m i n t h ( b c l k a l e ) t d ( b c l k r d ) 4 0n s . m a x t h ( r d a d ) t h ( b c l k r d ) 0 n s . m i n t d ( b c l k c s ) 4 0n s . m a x t h ( b c l k c s ) t h ( b c l k d b ) 4 n s . m i n t h ( w r d b ) t d ( d b w r ) t h ( b c l k a d ) t d ( a d a l e ) ( t c y c / 2 4 0 ) n s . m i n t d ( b c l k a d ) 4 0n s . m a x 4 0n s . m a x t h ( b c l k a l e ) 4 0n s . m a x t d ( b c l k w r ) t h ( b c l k w r ) t h ( w r a d ) t d ( b c l k d b ) 40 n s . m a x figure 4.6 timing diagram (5)
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 203 rev. 1.0 M306H2MC-XXXFP 5. items to be submitted when ordering masked rom version please submit the following when ordering masked rom products. (1) mask rom confirmation form (2) mark specification sheet (3) rom data : eproms (3 sets) or floppy disks *: in the case of eproms, there sets of eproms are required per pattern. *: in the case of floppy disks, 3.5-inch double-sided high-density disk (ibm format) is required per pattern.
204 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP 6. package outline lqfp116-p-2020-0.65 weight(g) e 1.78 jedec code eiaj package code lead material cu alloy 116p6a-a plastic 116pin 20 ? 20mm body lqfp e 0.125 e ee 0.2 e e ee e e e e e symbol min nom max a a 2 b c d e h e l l 1 y b 2 dimension in millimeters h d a 1 0.225 e e i 2 0.95 e e m d 20.4 e e m e 20.4 8
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 205 rev. 1.0 M306H2MC-XXXFP item processor mode rom type m1/m2 pin function cnv ss pin function byte pin function notes 1: microprocessor mode can be used only on M306H2MC-XXXFP. 2: these pins are used to control flash memory mode. for more information, consult m306h2fcfp flash memory specifications. 3 :when use flash memory mode (parallel i/o, standard serial i/o and cpu rewriting mode), connect with vss pin. 4 :since it differs in part about an electrical characteristics, check the specification of M306H2MC-XXXFP and m306h2fcfp. 5 :there are differences in electric characteristics, operation margin, noise immunity, and noise radiation between mask rom and flash memory version mcus due to the difference in the manufacturing processes. when manufacturing an application system with the flash memory version and then switching to use of the mask rom version, please perform sufficient evaluations for the commercial samples of the mask rom version. 6: before using the m306h2fcfp's standard serial input/output mode (boot mode) during, for example, application product development or mass-production startup, always refer to the pin connection diagrams and typical application circuits in figures 7.1 through 7.3. be careful at the time of mask rom development. M306H2MC-XXXFP single-chip mode memory extension mode microprocessor mode(note 1) mask rom m1: test input (connect it to the v ss pin.) m2: test input (connect it to the v ss pin.) this pin switches between processor modes. this pin switches between external data buses. m306h2fcfp single-chip mode memory expansion mode flash memory m1: chip mode setting input (note 2) m2: flash memory rewriting power supply input normally connect it to the v ss pin.(note 2) this pin switches between external data buses. (note 3) 7. differences between M306H2MC-XXXFP and m306h2fcfp
206 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP figure 7.1 pin connections for m306h2fcfp serial i/o mode byte x out vss x in vcc p8 7 /xc in p8 6 /xc out p8 1 /ta4 in p8 0 /ta4 o ut p7 7 /ta3 in cnvss p9 0 /tb0 in /clk3 p9 1 /tb1 in /s in 3 p9 2 /tb2 in /s out 3 p9 4 /da 1 /tb4 in p9 5 /anex0/clk4 p9 3 /da 0 /tb3 in p3 1 p4 2 p4 1 p4 0 p3 2 p3 3 p 3 4 p3 5 p 3 6 p3 7 v cc p4 3 p9 6 /anex1/s out 4 reset p8 5 /nmi p 8 4 /in t 2 p7 6 /ta3 out p7 5 /ta2 in p7 4 /ta2 out p7 2 /clk 2 /ta1 out p7 1 /r x d 2 /scl/ta0 in /tb5 in p7 3 /cts 2 /rts 2 /ta1 in p5 3 p5 6 p 4 4 p4 6 p4 7 p5 0 p5 1 p5 2 p5 4 p5 5 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 71 70 69 68 67 66 65 64 63 62 61 60 59 72 p0 7 p0 2 p0 3 p0 4 p0 5 p0 6 p0 0 p0 1 110 111 112 113 114 115 116 109 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 m306h2fcfp p8 3 /int 1 p8 2 /int 0 p6 1 /clk 0 p6 2 /r x d 0 p6 3 /t x d 0 p6 5 /clk 1 p6 6 /r x d 1 p6 7 /t x d 1 vref av ss p5 7 /clk out p6 0 /cts 0 /rts 0 p6 4 /cts 1 /rts 1 /clks 1 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 p11/sliceon m1 m2 v ss 1 v dd 1 p2 0 p2 7 p3 0 p2 6 p2 5 p2 4 p2 3 p2 2 p2 1 p1 4 p1 3 p1 2 p1 1 v ss p1 5 /int 3 p1 6 /int 4 p1 7 /int 5 p7 0 /t x d 2 /sda/ta0 out v ss 2 lp2 lp4 lp3 v dd 2 p1 0 p10 3 /an 3 p10 2 /an 2 p10 1 /an 1 p10 0 /an 0 av cc syncin cvin1 v dd 3 v ss 3 fscin p9 7 /adtrg/s in4 p4 5 p10 7 /an 7 /ki3 p10 4 /an 4 /ki0 p10 5 /an 5 /ki1 p10 6 /an 6 /ki2 svref vss vcc vss vcc (see note) reset vss vcc vss vpp sclk rxd txd busy vc c vss note. an oscillation circuit is connected. vss signal line name value cnvss vcc reset mode setting method m1 vss vss vcc vcc ce vcc ce
single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers 207 rev. 1.0 M306H2MC-XXXFP figure 7.2 example circuit application for m306h2fcfp standard serial i/o mode 1 rts 1 (busy) clk 1 r x d 1 t x d 1 cnvss clock input busy output data input data output m306h2 flash memory vpp power supply input nmi m2 m1 p5 0 (ce) byte (1) control pins and external circuitry will vary according to peripheral unit (programmer). for more information, see the peripheral unit (programmer) manual. (2) in this example, vpp source is supplied from the peripheral unit (programmer). when you use a user power supply, be sure to connect with 4.75v to 5.25v. (3) in this example, the processor mode (single-chip mode) and standard serial i/o mode are switched via a switch.
208 rev. 1.0 single-chip 16-bit cmos microcomputer with data acquisition controller mitsubishi microcomputers M306H2MC-XXXFP figure 7.3 example circuit application for m306h2fcfp standard serial i/o mode 2 busy clk 1 r x d 1 t x d 1 cnvss (1) in this example, vpp source is supplied from the peripheral unit (programmer). when you use a user power supply, be sure to connect with 4.75v to 5.25v. (2) in this example, the processor mode (single-chip mode) and standard serial i/o mode are switched via a switch. nmi m2 m1 p5 0 (ce) byte busy output data input data output vpp power supply input m306h2 flash memory
rev. rev. no. date 1.0 first edition 0202 M306H2MC-XXXFP data sheet (1/1) revision description revision description list

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